參數(shù)資料
型號(hào)： QL82SD-PQ208
廠商： Electronic Theatre Controls, Inc.
英文描述： 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps
中文描述： 10高速總線LVDS串行鏈路的帶寬高達(dá)5Gbps的
文件頁(yè)數(shù)： 25/60頁(yè)
文件大?。?/td> 3838K
代理商： QL82SD-PQ208
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
25
www.quicklogic.com
Figure 36: Input Register Cell
Table 24: Input Register Cell
Symbol
Input Register Cell Only
Parameter
Propagation
Delay (ns)
t
ISU
Input Register Setup Time: the amount of time the synchronous
input of the flip flop must be stable before the active clock edge.
3.12
t
IH
Input Register Hold Time: the amount of time the synchronous input
of the flip flop must be stable after the active clock edge.
0
t
ICLK
Input Register Clock to Q: the amount of time taken by the flip flop
to output after the active clock edge.
1.08
t
IRST
Input Register Reset Delay: the amount of time between when the
flip flop is
“
reset
”
(low) and when Q is consequently
“
reset
”
(low).
0.99
t
IESU
Input Register Clock Enable Setup Time: the amount of time
“
enable
”
must be stable before the active clock edge.
0.37
t
IEH
Input Register Clock Enable Hold Time: the amount of time
“
enable
”
must be stable after the active clock edge.
0
PAD
E
R
Q
D
+
-
TIN, TINI
TISU
TICLK
tSID
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