參數(shù)資料
型號(hào)： QL82SD-PQ208
廠商： Electronic Theatre Controls, Inc.
英文描述： 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps
中文描述： 10高速總線LVDS串行鏈路的帶寬高達(dá)5Gbps的
文件頁(yè)數(shù)： 28/60頁(yè)
文件大?。?/td> 3838K
代理商： QL82SD-PQ208
www.quicklogic.com
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
28
RAM Cell Synchronous Write Timing
Table 27: RAM Cell Synchronous Write Timing
Figure 41: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation
delay (ns)
t
SWA
WA setup time to WCLK: the amount of time the WRITE ADDRESS
must be stable before the active edge of the WRITE CLOCK
0.675
t
HWA
WA hold time to WCLK: the amount of time the WRITE ADDRESS
must be stable after the active edge of the WRITE CLOCK
0
t
SWD
WD setup time to WCLK: the amount of time the WRITE DATA must
be stable before the active edge of the WRITE CLOCK
0.654
t
HWD
WD hold time to WCLK: the amount of time the WRITE DATA must
be stable after the active edge of the WRITE CLOCK
0
t
SWE
WE setup time to WCLK: the amount of time the WRITE ENABLE
must be stable before the active edge of the WRITE CLOCK
0.623
t
HWE
WE hold time to WCLK: the amount of time the WRITE ENABLE must
be stable after the active edge of the WRITE CLOCK
0
t
WCRD
WCLK to RD (WA=RA): the amount of time between the active WRITE
CLOCK edge and the time when the data is available at RD
4.38
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD
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