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參數(shù)資料
| 型號： | QL80FC-APQ208I |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 757K |
| 代理商： | QL80FC-APQ208I |
9
QL80FC - QuickFC
TM
A wide range of additional features complements the
QL80FC device. The FPGA portion of the device is
5-volt and 3.3-volt compliant and can perform high-
speed logic functions such as 160 MHz FIFOs. I/O
pins provide individually controlled output enables,
dedicated input/feedback registers, and full JTAG
capability for boundary scan and test. In addition, the
QL80FC device provides the benefits of non-volatil-
ity, high design security, immediate functionality on
power-up, and a single chip solution.
The QL80FC customizable logic architecture consists
of an array of user-configurable logic building blocks,
called logic cells, set beneath a grid of metal wiring
channels similar to those of a gate array. Through
ViaLink
elements located at the wire intersections,
the output(s) of any cell may be programmed to con-
nect to the input(s) of any other cell. Using the cus-
tomizable logic in the QL80FC, designers can quickly
and easily customize their
“
back-end
”
design for any
number of applications.
FIGURE 4. Logic Cell
Array of Logic Cells
The QL80FC device has 22 1,152-bit RAM mod-
ules, for a total of 25,344 RAM bits. Using two
“
mode
”
pins, designers can configure each module
into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2
blocks. See the table below. The blocks are also eas-
ily cascadable to increase their effective width or
depth.
RAM Module Features
The RAM modules are
“
dual-ported
”
, with com-
pletely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports
support asynchronous and synchronous operation,
while the WRITE ports support synchronous opera-
tion. Each port has 18 data lines and 9 address lines,
allowing word lengths of up to 18 bits and address
spaces of up to 512 words. Depending on the mode
selected, however, some higher order data or address
lines may not be used.
A
RRAY
OF
L
OGIC
C
ELLS
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
QC
AZ
OZ
QZ
NZ
FZ
Mode:
Address
Buses [a:0]
[5:0]
[6:0]
[7:0]
[8:0]
Data Buses
[w:0]
[17:0]
[8:0]
[3:0]
[1:0]
64x18
128x9
256x4
512x2
RAM M
ODULE
F
EATURES
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