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參數(shù)資料
| 型號： | QL80FC-APQ208I |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 757K |
| 代理商： | QL80FC-APQ208I |
2
Preliminary
2
QL80FC - QuickFC
TM
FIGURE 1. System Level Diagram
General Description
The QL80FC device in the QuickLogic QuickFC ESP
(Embedded Standard Product) family provides a com-
pletely integrated configurable Fibre Channel
Encoder/Decoder interface solution combined with
customizable logic. This device provides a means to
receive and transmit high-speed serial data and
implement a Fibre Channel Link interface or any
proprietary high-speed serial link.
The chip is divided into two main portions, an
embedded design and a customizable design. The
embedded design contains the built in functionality of
Fibre Channel's FC-1 and FC-2 layers, which the sys-
tem designer uses as a standard product. This portion
can not be modified. As such, all functionality and
timing requirements have been verified in hardware
and are guaranteed.
The customizable portion consists of user customiz-
able system gates, and interfaces directly to the
embedded portion of the chip. These gates may be
programmed to implement glue logic to other bus
standards such as PCI or SCSI. They can also be pro-
grammed with Fibre Channel Upper Layer Protocols.
Of course, the designer may choose to modify Upper
Layer Protocols for customization. In this way, the
QuickLogic QL80FC provides the embedded systems
designer with an easy to use and cost effective solu-
tion for embedded serial applications.
Fibre Channel Application
The QL80FC ENDEC is a high performance
encoder/decoder designed for use in conjunction
with Gb/s SERDES transmitter/receiver chips. These
chips, when combined with internal FIFO buffer
memory, can be used to build a complete serial link.
Optional, external FIFOs can be used in place of the
available internal FIFOs to extend buffering to sizes
beyond 352 words.
The embedded ENDEC is a full duplex design with an
encoder section for transmission and a decoder sec-
tion for reception. The transmitter/encoder section
accepts a 4-byte user data word, encodes each byte
into a 10-bit transmission character and outputs
transmission characters to the SERDES transmitter.
This equals two 10-bit characters per clock (one 10-
bit character per clock in 10-bit mode). The receiver/
decoder section accepts two 10-bit transmission char-
System
Bus
(Optional)
Transmit
FIFO
(Optional)
Receive
FIFO
FIFO Control
User Customizable
Logic
Embedded
Fibre Channel
ENDEC
QL80FC Programmable ENDEC Chip
Bridge Logic
For Data Path
Transmit/
Receive
SERDES
2.5 Gb/s Serial
Data Over
Copper or
Optical Cable
Internal
Transmit
FIFO
Internal
Receive
FIFO
Micro-Processor
Or
System Bus
Interface
G
ENERAL
D
ESCRIPTION
F
IBRE
C
HANNEL
A
PPLICATIONS
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參數(shù)描述 |
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| QL8250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
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