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參數(shù)資料
| 型號： | QL80FC-APQ208I |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 19/21頁 |
| 文件大小： | 757K |
| 代理商： | QL80FC-APQ208I |
19
QL80FC - QuickFC
TM
AC CHARACTERISTICS at VCC = 3.3V, TA = 25
°
C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the
“
Operating Range
”
section by the following numbers.)
Logic Cells
RAM Cell Synchronous Write Timing
Notes:
[4] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25
°
C. Multiply by
the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating
Range.
[5] These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing analy-
sis of your particular design.
Symbol
Parameter
Propagation Delays (ns)
Fanout
[5]
2
1.7
1.9
1.7
1.7
0.0
0.0
1.0
1.2
1.2
1.2
1.2
1.2
1.3
1.5
1.1
1.3
1.9
1.9
1.8
1.8
1
3
4
8
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [6]
Setup Time [6]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
Symbol
Parameter
Propagation Delays (ns)
Fanout
[4]
2
1.0
1.0
0.0
0.0
1.0
1.0
0.0
0.0
1.0
1.0
0.0
0.0
5.3
5.6
1
3
4
8
TSWA
THWA
TSWD
THWD
TSWE
THWE
TWCRD
WA Setup Time to WCLK
WA Hold Time to WCLK
WD Setup Time to WCLK
WD Hold Time to WCLK
WE Setup Time to WCLK
WE Hold Time to WCLK
WCLK to RD (WA=RA) [4]
1.0
0.0
1.0
0.0
1.0
0.0
5.0
1.0
0.0
1.0
0.0
1.0
0.0
5.9
1.0
0.0
1.0
0.0
1.0
0.0
7.1
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