參數(shù)資料
型號(hào)： QL80FC-APQ208I
元件分類： 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁(yè)數(shù)： 6/21頁(yè)
文件大?。?/td> 757K
代理商： QL80FC-APQ208I
6
Preliminary
6
QL80FC - QuickFC
TM
When the RxRawEn signal is asserted the
“
raw
”
data
path will be enabled for the receive circuit. With the
“
raw
”
data path enabled, the data received from the
SERDES does not pass through the 8b/10b decoder
or the CRC checking blocks. Instead it is routed
directly to the output registers and is made available
to the customizable section of the chip on signal lines
RxRData and RxData. This mode is useful for testing
the serial link.
The Loss of Synchronization State machine is
responsible for achieving character synchronization
on the data being sent from the SERDES. When the
Rst signal is asserted, the LOSSM goes to the
“
loss of
synchronization
”
state. In this state the RxLOSync
signal will be asserted. After the reception of three
valid command characters, the state machine will
proceed to the
“
synchronization acquired
”
state and
the RxLOSync signal is de-asserted. After the recep-
tion of 4 successive invalid characters the state
machine will return to the
“
Loss of Synchronization
”
state. The value on the RxLOSIdx bus indicates the
state of LOSSM.
The ordered set recognition block detects Fibre
Channel ordered sets and asserts one signal line in
the RxSgpBus bus corresponding to the ordered set
detected. All 15 Fibre Channel ordered set types are
detected including SOF, EOF and IDLE. There is a list
of ordered sets detected by the ordered set recogni-
tion circuitry in Table 1.
There are two signals used to indicate that a word
having a decoding error of some kind is present on
the RxData outputs. When RxInvChar is asserted a
word with an invalid 10-bit representation is present
on the RxData signal lines. RxRDErr indicates an
invalid running disparity was detected on the cur-
rently available RxData word.
The Async_rst pin accepts an asynchronous, active
high reset signal. Circuitry takes this signal and syn-
chronizes it with the RxClk63 clock. This synchro-
nous reset signal, RxRst, is used to set or clear flip-
flops in the receive data path. It is made available to
the user programmable logic for the same purpose
on a high speed, low skew network.
The Clk_rst input stops the RxClk63 clock when this
signal is asserted. This signal was added primarily to
facilitate simulation. Clk_rst may be permanently
grounded in hardware.
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PDF描述
QL80FC Programmable Fibre Channel ENDEC(可編程光纖信道編解碼器)
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