- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224860 > PT7A4409L Complete Motion Control Verilog Library PDF資料下載
參數(shù)資料
| 型號： | PT7A4409L |
| 英文描述： | Complete Motion Control Verilog Library |
| 中文描述： | T1/E1/0C3系統(tǒng)同步？ |
| 文件頁數(shù)： | 9/34頁 |
| 文件大?。?/td> | 306K |
| 代理商： | PT7A4409L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Data Sheet
PT7A4402B/4402L
T1/E1 System Synchronizer
PT0100(08/02)
Ver:0
17
Capture Range: The PT7A4402B/4402L DPLL is not at present
in a state of synchronization (lock) with the incoming reference
signal, it is able to initiate (acquire) lock only if the signal’s fre-
quency is within a certain range, called the Capture Range. For
any PLL, no portion of the Capture Range can fall outside the
Lock Range, and, in general, the Capture Range is more narrow
than the Lock Range. However, owing to the design of its Phase
Detector, the PT7A4402B/4402L’s Capture Range is equal to its
Lock Range.
Phase Slope: Phase slope is measured in seconds per second
and is the rate at which a given signal changes phase with
respect to an ideal signal of constant frequency. The given
signal is typically the output signal. The ideal signal is of
constant frequency and is nominally equal to the value of the
final output signal or final input signal.
Time Interval Error (TIE): TIE is the time delay between a
given timing signal and an ideal timing signal.
Maximum Time Interval Error (MTIE): MTIE is the maxi-
mum peak to peak delay between a given timing signal and an
ideal timing signal within a particular observation period.
MTIE(S) = TIEmax(t) - TIEmin(t)
Phase Continuity: Phase continuity is the phase difference
between a given timing signal and an ideal timing signal at
the end of a particular observation period. Usually, the given
timing signal and the ideal timing signal are of the same fre-
quency. Phase continuity applies to the output of the synchro-
nizer after a signal disturbance due to a reference source switch
or a state change. The observation period is usually the time
from the disturbance, to just after the synchronizer has settled
to a steady state.
For the PT7A4402B/4402L, the output signal phase continu-
ity is maintained to within 5ns at the instance (over one frame)
of all reference source switches and all state changes. The total
phase shift, depending on the switch or type of state change,
may accumulate up to 200ns over many frames. The rate of
change of the 200ns phase shift is limited to a maximum phase
slope of approximately 5ns/125
s. This meets the AT&T
TR62411 maximum phase slope requirement of 7.6ns/125
s
(81ns/1.326ms).
J
T1o = JT1i x 10
= 20 x 10
= 2.5UI
J
E1o = JT1o x (
) = J
T1o x (
) = 3.3UI
Using the above method, the jitter attenuation can be calcu-
lated for all combinations of inputs and outputs based on the
three jitter transfer functions provided.
Note that the resulting jitter transfer functions for all combina-
tions of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs
(8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz,
16.384MHz) for a given input signal (jitter frequency and jit-
ter amplitude) are the same.
Since intrinsic jitter is always present, jitter attenuation will
appear to be lower for small input jitter signals than for large
ones. Consequently, accurate jitter transfer function measure-
ments are usually made with large input jitter signals (e.g.,
75% of the specified maximum jitter tolerance).
Frequency Accuracy: Frequency accuracy is defined as the
absolute tolerance of an output clock signal when it is not
locked to an external reference, but is operating in a free run-
ning mode. For the PT7A4402B/4402L, the Free-Run accu-
racy is equal to the Master Clock (OSCi) accuracy.
Holdover Accuracy: Holdover accuracy is defined as the ab-
solute tolerance of an output clock signal, when it is not locked
to an external reference signal, but is operating using storage
techniques. For the PT7A4402B/4402L the storage value is
determined while the device is in Normal State and locked to
an external reference signal. The absolute Master Clock (OSCi)
accuracy of the PT7A4402B/4402L does not affect Holdover
accuracy, but the change in OSCi accuracy while in Holdover
Mode does.
Lock Range: If the PT7A4402B/4402L DPLL is already in a
state of synchronization (“l(fā)ock”) with the incoming reference
signal, it is able to track this signal to maintain lock as its
frequency varies over a certain range, called the Lock Range.
The size of Lock Range is related to the range of the Digitally
Controlled Oscillators and is equal to 230ppm minus the ac-
curacy of the master clock (OSCi). For example, a 32ppm mas-
ter clock results in a Lock Range of 198ppm.
1UIT1
1UIE1
644ns
488ns
(
)
(
)
-A
20
-18
20
相關PDF資料 |
PDF描述 |
|---|---|
| PT7A4410 | PWM Waveform Generator Accelerator Verilog Module |
| PT7A4410L | Incremental Encoder Interface Accelerator Verilog Module |
| PT7A5020 | Power Diagnostics Function Accelerator Verilog Module |
| PT7A6525 | Reference design kit featuring a High Power Class D Audio Power Amplifier |
| PT7A6525L | 60V Single N-Channel HEXFET Power MOSFET in a TO-247AC package |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PT7A4410 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T1/E1/OC3 System Synchronizer |
| PT7A4410J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T1/E1/OC3 System Synchronizer |
| PT7A4410L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T1/E1/OC3 System Synchronizer |
| PT7A4410LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T1/E1/OC3 System Synchronizer |
| PT7A5020 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2048 Ports Non-Blocking Time-Slot Switch? |
發(fā)布緊急采購，3分鐘左右您將得到回復。