參數(shù)資料
型號(hào)： PT7A4409L
英文描述： Complete Motion Control Verilog Library
中文描述： T1/E1/0C3系統(tǒng)同步？
文件頁(yè)數(shù)： 7/34頁(yè)
文件大?。?/td> 306K
代理商： PT7A4409L
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Data Sheet
PT7A4402B/4402L
T1/E1 System Synchronizer
PT0100(08/02)
Ver:0
15
A simple way to control the Guard Time is shown in Figure 10.
The Guard Time can be calculated as follows:
V
CC
t
Gd = RC x ln (
)
RC x 0.6
V
CC - VSIH
* V
SIH is the logic high going threshold for the GTi Schmitt Trigger
input, see DC Electrical Characteristics.
Figure 10. Symmetrical Guard Time Circuit
In cases where fast toggling of the LOS1 input might be ex-
pected, an unsymmetrical Guard Time Circuit is recommended
as shown in Figure 11. This setting ensures that reference
switching does not occur until the entire guard time has ex-
pired. The timing diagram is shown in Figure 12.
Figure 11. Unsymmetrical Guard Time Circuit
Figure 12. Timing Example of Unsymmetrical Guard Time Circuit in Automatic Mode
Good
Bad
T
D
T
D
V
SIH
PRI
Normal
PRI
Holdover
SEC
Normal
PRI
Normal
PRI
Normal
PRI
Holdover
SEC
Signal
Status
LOS2
PRI
Signal
Status
LOS1
GTo
GTi
PT7A4402B
/4402L State
PT7A4402B/4402L
GTi
GTo
R
150k
R
P
1k
C
10
F
+
PT7A4402B/4402L
GTi
GTo
R
C
150k
R
P
1k
C
10
F
+
R
D
1k
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