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參數(shù)資料
| 型號： | PT7A5020 |
| 英文描述： | Power Diagnostics Function Accelerator Verilog Module |
| 中文描述： | 2048端口無阻塞時隙開關(guān)？ |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 51K |
| 代理商： | PT7A5020 |
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PT Pericom Technology Inc.
Preliminary Data Sheet
PT7A5020 Mult-Rate Large Digital Switch
1
PT0088(03/02)
Ver:0
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Features
Sixteen full-duplex, serial time-division
multiplexed (TDM) highway streams
Switching up to 2,048 incoming PCM channels
to up to 2,048 outgoing PCM channels
Accept data rates of 2.048Mb/s, 4.096Mb/s,
8.192Mb/s (Single-Rate mode) or any combination
of data rates of 2.048Mb/s, 4.096Mb/s and
8.192Mb/s (Multi-Rate mode)
64 kbits/s granularity with optional 32 kbits/s (4-
bit) and 16 kbits/s (2-bit) subrate switching
Tristate function per-channel for further
expansion
Low-latency/frame integrity selection per-channel
Automatic frame offset delay measurement.
Per input stream offset programming
Intel/Motorola microprocessor interface
Connection memory block programming for fast
device initialization
Automatically identifies ST-BUS/GCI formats
Internal loopback per-channel for diagnostic
purposes
IEEE-1149.1 (JTAG) boundary scan
Applications
Medium and large switching platforms
CTI application
Voice/data multiplexer
Digital cross-connect
ST-BUS/GCI interface functions
DM highway data rate adaptation
LAN/WAN gateways
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1
Introduction
The PT7A5020 is a Multi-rate Large Digital Switch
(MLDS). It provides 2,048 x 2,048 channel non-
blocking switching among 16 input streams and 16
output streams at most.
This device can operate in two modes: Single-Rate
mode and Multi-Rate mode. In Single-Rate mode, the
all 16 input streams and 16 output streams serial bit
rate must be single rate of 8.192Mb/s, 4.096Mb/s or
2.048Mb/s. In Multi-Rate mode, the 16 input streams
and the 16 output streams are both divided into two
parts, the serial bit rate of each one of the four parts
can be 8.192Mb/s, 4.096Mb/s or 2.048Mb/s
independently.
The device has many features that are programmable
on stream or channel basis, including message mode,
input offset delay and high impedance output control.
Per steam input delay control is particularly useful
for managing large multi-chip switches that transport
both voice channel and concatenated data channels.
In addition, input stream can be individually
calibrated for input frame offset using a dedicated
pin.
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相關(guān)代理商/技術(shù)參數(shù) |
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| PT7A6527 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad-channel Protocol Controller? | Demo board Schematic and Program?(PDF) |
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