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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD854F2V-15M

    

    
廠商：
STMICROELECTRONICS

    

    
元件分類：
微控制器/微處理器

    

    
英文描述：
256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52

    

    
封裝：
PLASTIC, QFP-52

    

    
文件頁(yè)數(shù)：
70/109頁(yè)

    

    
文件大?。?/td>
908K

    

    
代理商：
PSD854F2V-15M


    

    

    

	
    
    
    

    
    
	
    Obsolete
    Product(s)
    - Obsolete
    Product(s)
    63/109
    PSD813F2V, PSD854F2V
    Doc ID 10552 Rev 3
    Automatic Power-down (APD) Unit and Power-down Mode
    The APD Unit, shown in Figure 32, puts the PSD
    into Power-down mode by monitoring the activity
    of Address Strobe (ALE/AS, PD0). If the APD Unit
    is enabled, as soon as activity on Address Strobe
    (ALE/AS, PD0) stops, a four bit counter starts
    counting. If Address Strobe (ALE/AS, PD0) re-
    mains inactive for fifteen clock periods of CLKIN
    (PD1), Power-down (PDN) goes High, and the
    PSD enters Power-down mode, as discussed
    next.
    Power-down Mode. By default, if you enable the
    APD Unit, Power-down mode is automatically en-
    abled. The device enters Power-down mode if Ad-
    dress Strobe (ALE/AS, PD0) remains inactive for
    fifteen periods of CLKIN (PD1).
    The following should be kept in mind when the
    PSD is in Power-down mode:
    –
    If Address Strobe (ALE/AS, PD0) starts
    pulsing again, the PSD returns to normal
    Operating mode. The PSD also returns to
    normal Operating mode if either PSD Chip
    Select Input (CSI, PD2) is Low or the Reset
    (RESET) input is High.
    –
    The MCU address/data bus is blocked from all
    memory and PLDs.
    –
    Various signals can be blocked (prior to
    Power-down mode) from entering the PLDs by
    setting the appropriate bits in the PMMR
    registers. The blocked signals include MCU
    control signals and the common CLKIN (PD1).
    Note that blocking CLKIN (PD1) from the
    PLDs does not block CLKIN (PD1) from the
    APD Unit.
    –
    All PSD memories enter standby mode and
    are drawing standby current. However, the
    PLD and I/O ports blocks do not go into
    standby Mode because you don’t want to have
    to wait for the logic and I/O to “wake-up”
    before their outputs can change. See Table 28
    for Power-down mode effects on PSD ports.
    –
    Typical standby current is of the order of
    microamperes. These standby current values
    assume that there are no transitions on any
    PLD input.
    Table 28. Power-down Mode’s Effect on Ports
    Figure 32. APD Unit
    Table 29. PSD Timing and Standby Current during Power-down Mode
    Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
    2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’
    Port Function
    Pin Level
    MCU I/O
    No Change
    PLD Out
    No Change
    Address Out
    Undefined
    Data Port
    Tri-State
    Peripheral I/O
    Tri-State
    Mode
    PLD Propagation Delay
    Memory
    Access Time
    Access Recovery Time
    to Normal Access
    Typical Standby Current
    5V VCC
    3V VCC
    Power-down
    Normal tPD (Note
    1)
    No Access
    tLVDV
    75A (Note 2)
    25A (Note 2)
    APD EN
    PMMR0 BIT 1=1
    ALE
    RESET
    CSI
    CLKIN
    TRANSITION
    DETECTION
    EDGE
    DETECT
    APD
    COUNTER
    POWER DOWN
    (PDN)
    DISABLE BUS
    INTERFACE
    EEPROM SELECT
    FLASH SELECT
    SRAM SELECT
    PD
    CLR
    PD
    DISABLE
    FLASH/EEPROM/SRAM
    PLD
    SELECT
    AI02891
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD854F2V-90J
功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD854F2V-90M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD-8M-01
 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC

    

    
PSD913212JIT
 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD913212JT
 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
    
    
    
	
    	
    
    
     
     
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