參數(shù)資料
型號(hào)： PSD854F2V-15M
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： PLASTIC, QFP-52
文件頁數(shù)： 102/109頁
文件大?。?/td> 908K
代理商： PSD854F2V-15M
Obsolete
Product(s)
- Obsolete
Product(s)
PSD813F2V, PSD854F2V
92/109
Doc ID 10552 Rev 3
Table 58. WRITE Timing (3V devices)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Table 59. Program, WRITE and Erase Times (5V devices)
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Symbol
Parameter
Conditions
-12
-15
-20
Unit
MinMax
tLVLX
ALE or AS Pulse Width
26
30
tAVLX
Address Setup Time
(Note 1)
910
12
ns
tLXAX
Address Hold Time
(Note 1)
912
14
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1,3)
17
20
25
ns
tSLWL
CS Valid to Leading Edge of WR
(Note 3)
17
20
25
ns
tDVWH
WR Data Setup Time
(Note 3)
45
50
ns
tWHDX
WR Data Hold Time
(Note 3)
7
8
10
ns
tWLWH
WR Pulse Width
(Note 3)
46
48
53
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
10
12
17
ns
tWHAX2
Trailing Edge of WR to DPLD Address
Invalid
(Note 3,6)
000
ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
33
35
40
ns
tDVMV
Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear
(Notes 3,5)
70
80
ns
tAVPV
Address Input Valid to Address
Output Delay
(Note 2)
33
35
40
ns
tWLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes 3,4)
70
80
ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
Flash Program
8.5
s
Flash Bulk Erase1 (pre-programmed)
330
s
Flash Bulk Erase (not pre-programmed)
5
s
tWHQV3
Sector Erase (pre-programmed)
1
30
s
tWHQV2
Sector Erase (not pre-programmed)
2.2
s
tWHQV1
Byte Program
14
1200
s
Program / Erase Cycles (per Sector)
100,000
cycles
tWHWLO
Sector Erase Time-Out
100
s
tQ7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2
30
ns
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