參數(shù)資料
型號(hào)： PONE-000-01
廠商： Electronic Theatre Controls, Inc.
英文描述： The ideal device for simple nodes, such as switches, actuators and sensor
中文描述： 在簡(jiǎn)單的節(jié)點(diǎn)，如交換機(jī)，執(zhí)行器和傳感器的理想設(shè)備
文件頁(yè)數(shù)： 39/56頁(yè)
文件大?。?/td> 432K
代理商： PONE-000-01
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 39 of 56
(P3.2) is controlled by the PLSES. When GATE0 = 0, timer/counter 0 will only run if TCON.6 = 1 (software
control).
TMOD.2
C/NT0. Timer/Counter 0 selector. If 0, input is from internal system clock. If 1, input is from T0
pin. This bit
must
be set to 0 for correct operation of Timer 0, as pin T0 is output only.
TMOD.1
M1(0). Timer 0 Mode control bit M1.
TMOD.0
M0(0). Timer 0 Mode control bit M0.
For both timer counters the mode bits M0 and M1 apply as follows:
M1
0
0
1
1
M0
0
1
0
1
Operating Mode
13-bit timer/counter (M8048 compatible mode).
16-bit timer/counter.
8-bit auto-reload timer/counter.
Timer 0 is split into two halves. TL0 is an 8-bit
timer/counter controlled by the standard timer 0
control bits. TH0 is an 8-bit timer/counter
controlled by the standard timer 1 control bits.
TH1 and TL1 are held (Timer 1 is stopped).
Table 11 Configuration Mode Bits (TMOD.5, TMOD.4, TMOD.1, TMOD.0) for Timers 0 and 1
Timer/Counter Data (TL0 TL1 TH0 TH1)
TL0 and TH0 are the low and high bytes of timer/counter 0 respectively. TH0 and TH1 are the low and high
bytes of timer counter 1, respectively. On reset all timer/counter registers are 00 hex.
Timer/Counter 2 Control (T2CON)
Bit definitions for this register are as follows:
T2CON.7
TF2. Timer 2 overflow flag. Set by hardware when timer/counter 2 overflows unless either RCLK
or TCLK is set to 1. This bit is not cleared by hardware when the processor calls the interrupt service
routine.
T2CON.6
EXF2. Timer 2 external flag. This bit is set when a capture or reload is triggered by a negative
transition on T2EX (P1.1), and EXEN2 is set to 1. If Timer 2 interrupt is enabled, setting this bit will cause
an interrupt to the Timer 2 vector.
T2CON.5
RCLK. If this bit is set, the Serial Port receive clock is driven from the overflow pulses of Timer
2.
T2CON.4
TCLK. If this bit is set, the Serial Port transmit clock is driven from the overflow pulses of Timer
2.
T2CON.3
EXEN2. Timer 2 External interrupt enable flag. When set, a negative edge on T2EX (P1.1)
triggers a capture or auto-reload.
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