參數(shù)資料
型號(hào)： PONE-000-01
廠商： Electronic Theatre Controls, Inc.
英文描述： The ideal device for simple nodes, such as switches, actuators and sensor
中文描述： 在簡(jiǎn)單的節(jié)點(diǎn)，如交換機(jī)，執(zhí)行器和傳感器的理想設(shè)備
文件頁(yè)數(shù)： 32/56頁(yè)
文件大?。?/td> 432K
代理商： PONE-000-01
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 32 of 56
Example
The next page gives an example of an actual packet transmission. The six different values that are visible
in Figure 4 are the following:
CFM_EN: This signal is pulsed every time the PL-One firmware reads the Ph_Confirm_Reg. This is
roughly the same as when the PL-One firmware receives a PLSES Handshake Interrupt from the
PLSES (there is a small delay between receiving the interrupt and reading the Ph_Confirm_Reg.)
REQ_EN: This signal is pulsed every time the PL-One firmware writes to the Ph_Request_Reg. This
sends an interrupt to the PLSES, which then processes the value written into Ph_Request_Reg.
PH_CFM: This is the value in the Ph_Confirm_Reg.
PH_TX: This is the value in the Ph_Tx_Buffer.
PH_REQ: This is the value in the Ph_Request_Reg.
M_ST: This is the current medium state requested by the PLSES. This can take one of three values: 0
for INFERIOR, 1 for SUPERIOR Phase 1, and 2 for SUPERIOR Phase 2.
Note: the following explanation will mention several MACS state variables. If you are not familiar with these
variables, their definitions can be found in EIA 600.42.
You’ll notice that prior to beginning transmission there is a CFM_EN pulse every UST. This is the PLSES
Handshake Interrupt indicating that the channel is quiet, and should be used to increment the various
MACS transmission counters that are denominated in USTs. Once the Quiet counter is greater or equal to
Wait_Time, the PL-One firmware attempts a transmission by writing A6 hex to Ph_Request_Reg. This
requests a packet transmission including a full Preamble (since the
lzs
bit was not set.)
The PLSES receives the request, waits until an integral number of USTs have passed since the last time
either 00 hex or 20 hex was written to Ph_Request_Reg, and then begins transmission. As soon as
transmission begins, the PL-One firmware receives a PLSES Handshake Interrupt indicating that the
PLSES is ready for the next byte to transmit (Ph_Confirm_Reg = 10 hex). The PL-One firmware has right
up until the end of the transmission of the PEOF to respond to this interrupt by writing the control field to
Ph_Tx_Buffer, and B2 hex to Ph_Request_Reg. In this example a value of 0D hex is written to
Ph_Tx_Buffer, indicating that this is to be an ADR_ACK_DATA packet.
No collision occurs in this example, as at the end of the tranmission of the PEOF, the MDPS starts
transmitting the control field with leading zero suppression (as requested), and the PL-One firmware
receives a PLSES handshake interrupt indicating that the transmission buffer is ready for another byte.
This process continues through the DA, DHC, SA, SHC, and Data fields, right up until a request is made to
transmit the last data byte (09 hex) followed by an EOP symbol (A4 hex to Ph_Request_Reg). Since this
transmission information is stored in a one-byte buffer, another PLSES Handshake Interrupt is returned
when transmission of this final data byte begins. The PL-One firmware does not need to write to
Ph_Tx_Buffer for this interrupt, but does need to write A0 hex to Ph_Request_Reg to keep the
transmission going.
Once the EOP has been transmitted, it is followed by a 16-bit CRC. No PLSES Handshake Interrupt is
returned for this state transition. When the transmission of the CRC is finished, a final PLSES Handshake
Interrupt is returned, after which the PL-One firmware must write 00 hex to Ph_Request_Reg to return the
PLSES to its IDLE state. Interrupts will then be received every UST indicating that the channel is quiet, or
has become active.
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