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| 型號： | PONE-000-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The ideal device for simple nodes, such as switches, actuators and sensor |
| 中文描述： | 在簡單的節(jié)點，如交換機，執(zhí)行器和傳感器的理想設備 |
| 文件頁數(shù)： | 11/56頁 |
| 文件大?。?/td> | 432K |
| 代理商： | PONE-000-01 |
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March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 11 of 56
Bits in Ph_Confirm_Reg
Bit
Description
rx_del
1
rx_del
0
Description: Reception delimiters. In RCV state, this pair of
bits indicates the type of delimiter which terminates the current byte. Their
configuration is shown below in Table 4.
HW Reset state: 00
Enable trigger:
Set to 11 when a PEOF symbol has been detected and received.
Set to 10 when an EOP symbol has been detected and received. Also set
to 10 after the CRC has been received and the checksum result is
available, or set to 10 when the reception timestamp bytes are being
passed to the PL-One firmware.
Set to 01 when an EOF symbol has been detected and received.
Set to 00 when 8 consecutive packet Data symbols have been saved in
Ph_Rx_Buffer before receiving an EOF or EOP delimiter symbol. This
case can happen for any packet field part, including those transmitted with
Leading Zero Suppression (LZS). Also set to 00 when a PEOF symbol
has been received but fewer than 8 Preamble symbols were detected.
This situation is likely to happen with a Medium Noisy indication (see
ch_noisy
bit).
Reset trigger: It is reset when the PLSES Handshake Interrupt is reset.
jabber (LSB)
Description: Jabber Detect. In XMIT state, it indicates that the
PL-One has transmitted at least 1,000 consecutive SUPERIOR symbols. In
RCV state, it indicates that the PL-One has received at least 1,000
consecutive SUPERIOR symbols.
HW Reset state: 0
Enable trigger: Set to 1 after the PL-One has transmitted at least 1,000
consecutive SUPERIOR symbols. Also set to 1 after the PL-One has
received at least 1,000 consecutive SUPERIOR symbols.
Reset trigger: It is reset when 1024 consecutive SUPERIOR states have
been detected on the channel in either transmission or reception.
Table 3 Explanation of Bits in Ph_Confirm_Reg SFR
Symbol
del
1
del
0
# USTs
EOF
0
1
3
EOP
1
0
4
PEOF
1
1
8
No delimiter
0
0
0
Table 4 Bit Representation of Four Possible Delimiters (EOF, EOP, PEOF, and none)
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