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| 型號： | PONE-000-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The ideal device for simple nodes, such as switches, actuators and sensor |
| 中文描述： | 在簡單的節(jié)點，如交換機，執(zhí)行器和傳感器的理想設(shè)備 |
| 文件頁數(shù)： | 37/56頁 |
| 文件大?。?/td> | 432K |
| 代理商： | PONE-000-01 |
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March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 37 of 56
Timer/Counter 2 low byte
Timer/Counter 2 high byte
Program Status Word
Confirm Port from PLSES
TL2
TH2
PSW
CC
CD
D0
D8*
ü
ü
PH_CONFIRM_
REG
A
PH_REQUEST_
REG
B
Accumulator
Request Port to PLSES
E0
E8*
ü
ü
B Register
F0
ü
Table 10 M8052 SFR Map
Note that the registers marked * are not present in the original device.
SFR Definitions
I/O Ports (P0 P1 P2 P3)
P0, P1, P2, P3.0 and P3.1 are latches used to drive the 26 quasi-bidirectional I/O lines. On reset they are
all set to the FF hex value, which is input mode. P3.3 and P3.5 are always in input mode; writing these
bits has no effect on the external port or on the next value read from these bits. P3.4, P3.6 and P3.7 are
always in output mode. External voltages applied to these pins can not be read from within the chip.
Stack Pointer (SP)
The SP register contains the stack pointer. The stack pointer is used to load the program counter into
memory during LCALL and ACALL instructions and is used to retrieve the program counter from memory
in RET and RETI instructions. Temporary data may also be saved or loaded using PUSH and POP
instructions, which also increment and decrement the stack pointer. The stack pointer points to the top
location of the stack. On reset the stack pointer is set to 07 hex.
Data Pointer (DPTR)
The Data Pointer (DPTR) is 16 bits in size and consists of two registers, the Data Pointer High byte (DPH),
and the Data Pointer Low byte (DPL). Two 16-bit operations are possible on this register, they are load
immediate and increment. This register is used for 16-bit address external memory accesses, for offset
code byte fetches and for offset program jumps. On reset, the value of this register is 0000 hex.
Power Control Register (PCON)
Bit definitions for this register are as follows:
PCON.7
SMOD. Double baud rate bit. For use see below.
PCON.6
Not implemented.
PCON.5
Not implemented.
PCON.4
Not implemented.
PCON.3
GF1. General purpose flag bit.
PCON.2
GF0. General purpose flag bit.
PCON.1
Not implemented.
PCON.0
IDL. Idle bit. If 1, Idle mode is entered.
On reset this register returns 0XXX0000 binary.
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