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| 型號： | PONE-000-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The ideal device for simple nodes, such as switches, actuators and sensor |
| 中文描述： | 在簡單的節(jié)點，如交換機，執(zhí)行器和傳感器的理想設(shè)備 |
| 文件頁數(shù)： | 31/56頁 |
| 文件大小： | 432K |
| 代理商： | PONE-000-01 |
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March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 31 of 56
Timing Constraints
It is important to note that the PLSES sends an interrupt to the PL-One firmware every UST (100
μ
s) when
there isn’t any activity on the channel. This interrupt is required if the firmware is to accurately implement
the timing constraints specified within the EIA documents on the DLL and MACS (EIA 600.41, 600.42).
However it places some severe restrictions on the design of the interrupt service routine. This routine
should never last more than 100
μ
s when in the IDLE state, as an interrupt will then be missed. If possible,
it should be considerably shorter than this, so as to allow as much processing time for other processes
when the channel is quiet.
Transmission Timing Constraints
The PLSES uses a one-byte transmission buffer (in addition to Ph_Tx_Buffer) to store the byte that is
currently being transmitted. This gives the PL-One firmware some breathing room, as it has between 3
and 26 USTs to write the next byte to the Ph_Tx_Buffer before an underrun condition will occur. For
example, when starting transmission, the byte 101X 0000 bin is written to Ph_Request_Reg. As soon as
the PLSES starts transmitting the Preamble (or PEOF, if the
lzs
bit was set), it returns a PLSES
Handshake Interrupt with the Ph_Confirm_Reg set to 10 hex. The PL-One firmware then has up to the end
of the transmission of the PEOF to respond to this Interrupt before an underrun condition will occur. The
worst-case scenario in the CEBus standard is when a 00 hex byte is transmitted with leading zero
suppression, and an EOF delimiter. Since an EOF takes 3 USTs to transmit, the PL-One firmware has
300
μ
s to send another byte down to the PLSES before an underrun condition will occur.
Reception Timing Constraints
The reception timing constraints are similar to the constraints in transmission. The PL-One firmware must
ensure that it completes all PLSES Handshake Interrupts within 3 USTs to avoid the possibility of an
overrun condition (ex: two EOF symbols immediately after each other, which will occur for any packets
sent to the broadcast address.) A much tighter constraint, however, is the CEBus standard requirement
that IACK, FAILURE, and ADR_IACK packets be transmitted within 2 USTs of ACK_DATA or
ADR_ACK_DATA packets addressed to your local address. It is recommended that the appropriate
packet be assembled as soon as it is detected that an acknowledged packet is addressed to you, and that
the transmission of this packet should be started in the RCV_STAMP PLSES Handshake Interrupt. This
interrupt indicates that the CRC has been received and that the least significant timestamp byte is available
in Ph_Rx_Buffer.
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