參數(shù)資料
型號(hào)： PNX8510
廠商： NXP Semiconductors N.V.
英文描述： Analog companion chip
中文描述： 模擬伴隨芯片
文件頁(yè)數(shù)： 57/92頁(yè)
文件大小： 3064K
代理商： PNX8510
Philips Semiconductors
PNX8510/11
Analog companion chip
Product data
Rev. 04 – 12 January 2004
57 of 92
9397 750 12612
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7
Y_TOCO
R/W
0
Y Two’s complement <-> binary offset conversion
0 = Data at the output of the HD-data path are left unchanged
1 = MSB of data output of the HD-data path is inverted
U Two’s complement <-> binary offset conversion
0 = Data at the output of the HD-data path are left unchanged.
1 = MSB of data output of the HD-data path is inverted.
V Two’s complement <-> binary offset conversion
0 = Data at the output of the HD-data path are left unchanged.
1 = MSB of data output of the HD-data path is inverted.
Enables insertion of R/Y sync signals into the component signals.
0 = Embedded sync is disabled.
1 = Embedded sync is enabled.
Enables insertion of G/U sync signals into the component signals.
0 = Embedded sync is disabled.
1 = Embedded sync is enabled.
Enables insertion of B/V sync signals into the component signals.
0 = Embedded sync is disabled.
1 = Embedded sync is enabled.
Sync signal insertion enable
0 = No insertion of HD sync module generated sync signals - the
external signals are forwarded to the sync ports.
1 = The insertion of HD sync module generated H-sync, V-sync and
Blank signals is enabled. (Note: This disables external sync
signals.)
H-sync is derived from sync value[0].
V-sync is derived from sync value[1].
C-blank is derived from sync value[2].
Enable 422 to 444 up-sampling filter
0 = Filter switched into bypass mode
1 = Filter is active.
6
U_TOCO
R/W
0
5
V_TOCO
R/W
0
4
Y/R_SYNC_INS_EN
R/W
0
3
U/G_SYNC_INS_EN
R/W
0
2
V/B_SYNC_INS_EN
R/W
0
1
SYNC_SIG_EN
R/W
0
0
UPSAMPLE_EN
R/W
0
Offset 0xA6 - DAC6_ADJ*
7:5
Unused
4:0
DAC6_ADJ
Offset 0xA7 - DAC5_ADJ*
7:5
Unused
4:0
DAC5_ADJ
Offset 0xA8 - DACC_ADJ*
7:4
Unused
3:0
DACC_ADJ
Offset 0xA7 - SYNC_DELAY
7
VBIPROG
-
0
R/W
DAC6 output level coarse adjustment
-
0
R/W
DAC5 output level coarse adjustment
-
0
R/W
DAC5 and 6 output level fine adjustment
0
0 = Programming via VBI disabled (use this mode for 24-bit parallel
mode and any other mode containing non-656 compliant data).
1 = Programming via VBI enabled
6:3
Unused
-
Table 29:
* indicates not present in secondary video channel
Bit
Symbol
PNX8510/11 video registers
…continued
Access Value
Description
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