參數(shù)資料
型號(hào)： PNX8510
廠(chǎng)商： NXP Semiconductors N.V.
英文描述： Analog companion chip
中文描述： 模擬伴隨芯片
文件頁(yè)數(shù)： 13/92頁(yè)
文件大小： 3064K
代理商： PNX8510
Philips Semiconductors
PNX8510/11
Analog companion chip
Product data
Rev. 04 – 12 January 2004
13 of 92
9397 750 12612
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The normal mode of operation is that the DV1 interface is routed to the primary video
data paths and the DV2 interface is routed to the secondary video data paths. The IC
however accepts also so called sliced data formats. A sliced data format contains two
single video data streams multiplexed together on a component basis. A more
detailed description of the arrangement of the components can be found in
Section 7.1.2
. To enable sliced data formats the SLICE_MODE bit of the register
VMUXCTL (register offset 0x95) has to be set.
The De-Slice module essentially takes the two data streams apart by simply two to
one de-multiplexing. The routing of the resulting two video data streams is
determined by setting the SEL register bits in the primary and secondary video data
path apertures appropriately. Sliced data formats come in two different flavors: double
edge and qualified.
The double edge slice format has data changes on the positive and the negative
clock edge where as the qualified mode qualifies one data stream of the two
multiplexed ones with an active high on the HSYNC signal. To use this mode the
USE_QUALIFIER bit in the register INPCTL (offset 0x3A) must be set. The order of
the slice qualification can be changed by setting the QUAL_INVERT bit of the same
register (offset 0x3A).
Since each of the video input interfaces can accept sliced data formats a total of four
video data streams could be routed into the IC and two of them can be selected to be
forwarded to the primary and the secondary video display pipeline.
The structure of the video input module is shown in
Figure 11
.
Fig 11. Block diagram - video input module
MDB645
RST SYNC
PRIMARY
RST SYNC
SECONDARY
REGISTER ARRAY PRIMARY
REGISTER ARRAY SECONDARY
OUT-
SEL
OUT-
SEL
DE-SLICE
VBI DATA SLICER
VBI DATA SLICER
DE-SLICE
OUTPUT
FORMATTER
DEMUX_MODE
R/Y/Y
G/U/U-V
B/V
Y
U - V
OUTPUT
FORMATTER
SAV-EAV
DETECTION
SAV-EAV
DETECTION
DEMUX_MODE
8/10-bit mode
data 1
input
D1-IN
secondary
SEL1
SEL2
TTX data port
TTX data port
SLICE_MODE
O_E
O_E
SLICE_DIR
SLICE_MODE
SLICE_DIR
8/10-bit mode
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