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參數(shù)資料
| 型號： | PNX3000N3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Analog front end for digital video processors |
| 中文描述： | 模擬前端數(shù)字視頻處理器 |
| 文件頁數(shù)： | 19/51頁 |
| 文件大?。?/td> | 285K |
| 代理商： | PNX3000N3 |
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2004 Oct 04
19
Philips Semiconductors
Preliminary specification
Analog front end for digital video
processors
PNX3000
Table 41
Clamp mode secondary CVBS channel
Table 42
Clamp mode primary CVBS channel
Table 43
Selection of CVBS output A
Table 44
Mute SCART2 audio output
Table 45
Mute SCART1 audio output
Table 46
Mute LINE audio output
Table 47
Selection of CVBS output B
Table 48
Selection of RGB/YUV input
Table 49
RGB/YUV input mode
Notes
1.
YUV input is an Y,
(B
Y) and
(R
Y) input with the
specification:
a) Y = 1.43 V (p-p); U = 1.33 V (p-p);
V = 1.05 V (p-p).
b) These signal amplitudes are based on a colour bar
signal with 75 % saturation.
YPbPr input with the specification:
a) Y = 1.0 V (p-p); Pb = 0.7 V (p-p); Pr = 0.7 V (p-p).
b) These signal amplitudes are based on a colour bar
signal with 100 % saturation.
RGB input with the specification:
a) R = 0.7
×
V
B-W
; G = 0.7
×
V
B-W
; B = 0.7
×
V
B-W
.
b) These signal amplitudes are based on a colour bar
signal with 100 % saturation.
2.
3.
CMS
MODE
0
1
top sync clamping mode
black level clamping mode
CMP
MODE
0
1
top sync clamping mode
black level clamping mode
CVA3
CVA2
CVA1
CVA0
SELECTED
SIGNAL
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
CVBS_IF
CVBS1
CVBS2
CVBS3
Y + C3
CVBS4
Y + C4
CVBS_DTV
output muted
other
MA2
MODE
0
1
normal operation
SCART2 audio output muted
MA1
MODE
0
1
normal operation
SCART1 audio output muted
MA0
MODE
0
1
normal operation
LINE audio output muted
CVB3
CVB2
CVB1
CVB0
SELECTED
SIGNAL
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
CVBS_IF
CVBS1
CVBS2
CVBS3
Y + C3
CVBS4
Y + C4
CVBS_DTV
output muted
other
RSEL
SELECTED SIGNAL
0
1
RGB1 input
RGB2 input
MAT
DVD
MODE
0
0
1
1
0
1
0
1
YUV input; note 1
YPbPr input; note 2
RGB input; note 3
spare
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