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參數(shù)資料
| 型號： | PNX3000N3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Analog front end for digital video processors |
| 中文描述： | 模擬前端數(shù)字視頻處理器 |
| 文件頁數(shù)： | 18/51頁 |
| 文件大?。?/td> | 285K |
| 代理商： | PNX3000N3 |
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2004 Oct 04
18
Philips Semiconductors
Preliminary specification
Analog front end for digital video
processors
PNX3000
Table 30
Group delay correction
Table 31
2nd SIF LPF mode
Table 32
Bypass anti-alias filters of secondary CVBS
Table 33
Sound trap frequency
Table 34
Data link transmitter test mode
Note
1.
The pseudo random mode can be used for in-circuit
testing of the data link connections between data link
transmitter in the analog front end IC and data link
receiver in the digital video processor IC.
Table 35
YUV 2f
H
clamp pulse timing
Table 36
Data link modes; note 1
Note
1.
See Table 2 in Chapter “Functional description”.
Table 37
Selection of secondary video signal
Table 38
Selection of primary video channel
Table 39
Video ident mode
Table 40
IF video mute
GD
MODE
0
1
group delay correction bypass
group delay correction active
SLPM
MODE
0
1
2nd SIF LPF active
2nd SIF LPF bypass (for FM radio 10.7 MHz)
BPS
MODE
0
1
normal operation
secondary CVBS anti-alias filters bypass
ST1
ST0
FREQUENCY
0
0
1
1
0
1
0
1
5.5 MHz
4.5 MHz
6.0 MHz
6.5 MHz
DRND
MODE
0
1
normal operation
pseudo random test mode; note 1
HDTV
MODE
0
1
normal timing (480p signal)
HDTV timing (1080i signal)
DM
APPLICATION
MODE
0
1
Normal
YUV 2f
H
0
1
SEC3
SEC2
SEC1
SEC0
SELECTED
SIGNAL
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
CVBS_IF
CVBS1
CVBS2
CVBS3
Y + C3
CVBS4
Y + C4
CVBS_DTV
CVBS_IF
other
PRI3
PRI2
PRI1
PRI0
SELECTED
SIGNAL
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
CVBS_IF
CVBS1
CVBS2
CVBS3
Y + C3
CVBS4
Y + C4
YC_COMB
CVBS_IF
other
VIM
MODE
0
1
ident coupled to CVBS_IF
ident coupled to selected primary CVBS signal
VSW
MODE
0
1
normal operation
CVBSOUTIF muted
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