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參數(shù)資料
| 型號(hào)： | PNX3000N3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Analog front end for digital video processors |
| 中文描述： | 模擬前端數(shù)字視頻處理器 |
| 文件頁數(shù)： | 17/51頁 |
| 文件大小： | 285K |
| 代理商： | PNX3000N3 |
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2004 Oct 04
17
Philips Semiconductors
Preliminary specification
Analog front end for digital video
processors
PNX3000
Table 19
IFAGC operation mode
Note
1.
Gated operation improves weak signal performance.
Gated operation is automatically disabled if CVBS_IF
is not selected as primary or secondary video signal.
In this situation bit IFLH should be set to 1 to avoid
recalibration of the IF VCO for white video patterns.
Table 20
CVBS IF output signal amplitude correction for
system I
Table 21
IF PLL offset adjustment
Table 22
CVBS IF output signal amplitude
Table 23
IFAGC tuner take over
Table 24
External reference frequency
Table 25
PLL demodulator frequency setting
Table 26
IF VCO synthesizer frequency (SF7 to SF0);
note 1
Note
1.
f
synth
= (N + 1)
×
250 kHz; where 95
≤
N
≤
255.
Table 27
Bypass UV anti-alias filters
Table 28
Bypass Y
yuv
anti-alias filter
Table 29
Bypass anti-alias filters of primary CVBS
IFGT
MODE
0
1
non gated operation
gated operation; note 1
VAI
MODE
PMOD = 0
PMOD = 1
0
1
no correction
amplitude +8 %
no correction
amplitude
8 %
IFO5 TO IFO0
(HEX)
CONTROL
00
20
3F
tbf
no correction
tbf
VA1
VA0
OUTPUT SIGNAL AMPLITUDE
PMOD = 0
PMOD = 1
0
0
1
1
0
1
0
1
no correction
spare
amplitude
5 %
amplitude +5 %
no correction
spare
amplitude +5 %
amplitude
5 %
TTO5 TO TTO0
(HEX)
CONTROL
3F
tuner take over at IF input signal of
0.4 mV
tuner take over at IF input signal of
80 mV
00
FXT
CONDITION
0
1
13.5 MHz
27 MHz
IFA
IFB
IFC
IF FREQUENCY
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
58.75 MHz
45.75 MHz
38.90 MHz
38.00 MHz
33.40 MHz
33.90 MHz
SF7 TO SF0
(DECIMAL
NUMBER)
FREQUENCY
95
255
f = 24 MHz
f = 64 MHz
BPUV
MODE
0
1
normal operation
UV anti-alias filters bypass
BPY
MODE
0
1
normal operation
Y
yuv
anti-alias filter bypass
BPP
MODE
0
1
normal operation
primary CVBS anti-alias filters bypass
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