PNX1300/01/02/11 Data Book
Philips Semiconductors
15-2
PRELIMINARY SPECIFICATION
The command was completed with no exceptions
A start code was detected
An error was encountered in the bitstream
The VLD input DMA completed, and the VLD is
stalled waiting for more data
One of the VLD output DMAs has completed and the
VLD is stalled because the output FIFO is full
The DSPCPU can be interrupted whenever the VLD
halts.
Consider the case in which the VLD has encountered a
start code. At this point, the VLD will halt and set the sta-
tus flag to indicate that a start code has been detected.
This event will generate an interrupt to the DSPCPU (if
corresponding interrupt is enabled). Upon entering the
interrupt routine, the DSPCPU will read the VLD status
register to determine the source of the interrupt. Once it
has determined that a start code was encountered, the
CPU will read 8 bits from the VLD shift register to deter-
mine the type of start code encountered. If it a
‘
slice
’
start
code, the DSPCPU reads from the shift register the slice
quantization scale and any extra slice information. The
slice quantization scale is then written back to the VLD
quantizer-scale register. Before exiting the interrupt rou-
tine, the DSPCPU will clear the start code detected sta-
tus bit in the status register and issue a new command to
process the remaining macroblocks.
15.3
DECODING UP TO A SLICE
MPEG decoding up to the slice layer is carried out by the
DSPCPU and the VLD. The VLD is controlled by the
DSPCPU for the decoding of all parameters up to the
slice-start code. During this process, the DSPCPU reads
from the VLD_SR register which contains the next 16 bits
of the bitstream. The DSPCPU also issues shift com-
mands to the VLD in order to advance the contents of the
shift register by the specified number of bits. The
DSPCPU may also command the VLD to advance to the
next start code. Refer to
Table 15-6
for a complete list of
VLD commands and their functions. Once at the slice
layer, the VLD operates independently for the entire slice
decoding. The slice decoding starts once the DSPCPU
issues a
parse
command.
15.4
VLD INPUT
Input to the VLD is controlled by the VLD input DMA en-
gine. The input DMA engine is programmed by the
DSPCPU to read from SDRAM. The DSPCPU programs
this DMA engine by writing the address and the length of
the SDRAM buffer containing the MPEG stream. The ad-
dress of the buffer is written to the VLD_BIT_ADR regis-
ter. The length, in bytes, of the buffer is written to the
VLD_BIT_CNT register.
Esc Count
MBA Inc
MB Type
Mot Type DCT Type
MV count
MV Format
DMV
MV Field Sel [0][0]
Motion Code [0][0][1]
Motion Residual [0][0][0]
Motion Residual [0][0][1]
Motion Code [0][0][0]
MV Field Sel [1][0]
Motion Code [1][0][1]
Motion Residual [1][0][0]
Motion Residual [1][0][1]
Motion Code [1][0][0]
MV Field Sel [0][1]
Motion Code [0][1][1]
Motion Residual [0][1][0]
Motion Residual [0][1][1]
Motion Code [0][1][0]
MV Field Sel [1][1]
Motion Code [1][1][1]
Motion Residual [1][1][0]
Motion Residual [1][1][1]
Motion Code [1][1][0]
quant scale
CBP
dmvector[0]
dmvector[1]
31
First Forward Motion Vector
30
31
Second Forward Motion Vector (for MPEG2 only)
30
31
First Backward Motion Vector
30
31
Second Backward Motion Vector (for MPEG2 only)
30
31
0
1
2
3
4
6
11
17
25
7
15
23
29
13
7
15
23
29
13
7
15
23
29
13
7
15
23
29
13
4
10
12
14
31
Figure 15-2. MPEG-2 macroblock header output format
w1
w2
w3
w4
w5
w0
M
M