參數(shù)資料
型號(hào): PLL1700E
英文描述: MULTI-CLOCK GENERATOR
中文描述: 多時(shí)鐘發(fā)生器
文件頁(yè)數(shù): 2/9頁(yè)
文件大?。?/td> 137K
代理商: PLL1700E
2
PLL1700
SPECIFICATIONS
All specifications at T
A
= +25
°
C, V
DD
= V
DDP
= +5V, V
DDB
= +3.3V, f
M
= 27MHz crystal oscillation and f
S
= 48kHz, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PLL1700E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT/OUTPUT
Input Logic Level:
V
IH
V
IL
Input Logic Current:
I
IH(1)
I
IL(1)
I
IH(2)
I
IL(2)
Output Logic Level:
V
OH(3)
V
OL(3)
Sampling Frequency (f
S
)
TTL-Compatible
2.0
VDC
VDC
0.8
V
IN
= V
DD
V
IN
= 0V
V
IN
= V
DD
V
IN
= 0V
200
–1
4
–800
μ
A
μ
A
mA
μ
A
CMOS
I
OH
= 4mA
I
OL
= 4mA
Standard f
S
Double f
S
V
DDB
– 0.4V
VDC
VDC
kHz
kHz
0.4
48
96
32
64
44.1
88.2
MASTER CLOCK (MCKO, MCKO)
Master Clock Frequency
Clock Jitter
(4)
Clock Duty Cycle
For Crystal Oscillation
Clock Duty Cycle
For External Clock
f
M
= 27MHz, C
L
= 20pF
26.73
27
300
50
50
40
60
27.27
MHz
ps
%
%
%
%
MCKO
MCKO
MCKO
MCKO
40
40
60
60
PHASE LOCK LOOP (PLL)
Generated System Clock Frequency
SCKO1
SCKO2
SCKO3
SCKO4
Generated Clock Rise Time
(3)
Generated Clock Fall Time
(3)
Generated Clock Duty Cycle
f
M
= 27MHz, C
L
= 20pF
Fixed
256f
S
384f
S
768f
S
33.8688
MHz
MHz
MHz
MHz
ns
ns
%
%
%
ps
ps
ps
ms
ms
8.192
12.288
24.576
24.576
36.864
36.864
20% to 80% V
DDB
80% to 20% V
DDB
SCKO1, SCKO3, SCKO4
SCKO2 (standard)
SCKO2 (double)
(5)
SCKO1, SCKO2 (standard), SCKO4
SCKO3
SCKO2 (double)
To Programmed Frequency
To Programmed Frequency
5
5
50
50
33
300
150
450
40
40
25
60
60
40
Generated Clock Jitter
(4)
Settling Time
Power-Up Time
20
30
15
POWER SUPPLY REQUIREMENTS
Voltage Range
V
DD
, V
DDP
V
DDB
+4.5
+2.7
+5
+3.3
+5.5
+3.6
VDC
VDC
Supply Current
(6)
:
I
DD
+ I
DDP
I
DDB
Power Dissipation
V
DD
= V
DDP
= 5V, f
S
= 48kHz
V
DDB
= +3.3V, f
S
= 48kHz
f
S
= 48kHz
11
6
75
16
9
110
mA
mA
mW
TEMPERATURE RANGE
Operation
Storage
–25
–55
+85
+125
°
C
°
C
NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor). (2) XT1, when an external 27MHz clock is used, the buffer ICs, such
as 74HC04, are recommended to interface to XT1. (3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1. (4) Jitter performance is specified as standard
deviation of jitter under 27MHz crystal oscillation. (5) When SCKO2 is set to double rate clock output, its duty cycle is 33%. (6) f
M
= 27MHz crystal oscillation, no
load on MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.
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