參數(shù)資料
型號(hào): PIC18F45J50-I/ML
廠商: Microchip Technology
文件頁數(shù): 159/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 2V 44-QFN
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 45
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F46J50 FAMILY
DS39931D-page 94
2011 Microchip Technology Inc.
ANCON1
VBGEN
r
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
00-0 0000
ANCON0
PCFG7(5)
PCFG6(5)
PCFG5(5)
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000 0000
ODCON1
ECCP20D
ECCP10D ---- --00 74, 134
ODCON2
U2OD
U1OD
---- --00
ODCON3
SPI2OD
SPI1OD
---- --00
RTCCFG
RTCEN
RTCWREN RTCSYNC
HALFSEC
RTCOE
RTCPTR1
RTCPTR0 0-00 0000 74, 227
RTCCAL
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
0000 0000
REFOCON
ROON
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
0-00 0000
PADCFG1
RTSECSEL1 RTSECSEL0
PMPTTL
---- -000
UCFG
UTEYE
UOEMON
UPUEN
UTRDIS
FSEN
PPB1
PPB0
00-0 0000
UADDR
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
-000 0000
UEIE
BTSEE
BTOEE
DFN8EE
CRC16EE
CRC5EE
PIDEE
0--0 0000
UIE
SOFIE
STALLIE
IDLEIE
TRNIE
ACTVIE
UERRIE
URSTIE
-000 0000
UEP15
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP14
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP13
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP12
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP11
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP10
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP9
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP8
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP7
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 74, 364
UEP6
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 75, 364
UEP5
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 75, 364
UEP4
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 75, 364
UEP3
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 75, 364
UEP2
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 75, 364
UEP1
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 75, 364
UEP0
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL ---0 0000 75, 364
PPSCON
—IOLOCK
---- ---0
RPINR24
Input Function FLT0 to Input Pin Mapping Bits
---1 1111
RPINR23
Input Function SS2 to Input Pin Mapping Bits
---1 1111
RPINR22
Input Function SCK2 to Input Pin Mapping Bits
---1 1111
RPINR21
Input Function SDI2 to Input Pin Mapping Bits
---1 1111
RPINR17
Input Function CK2 to Input Pin Mapping Bits
---1 1111
RPINR16
Input Function RX2DT2 to Input Pin Mapping Bits
---1 1111
RPINR13
Input Function T3G to Input Pin Mapping Bits
---1 1111
RPINR12
Input Function T1G to Input Pin Mapping Bits
---1 1111
RPINR8
Input Function IC2 to Input Pin Mapping Bits
---1 1111
RPINR7
Input Function IC1 to Input Pin Mapping Bits
---1 1111
RPINR6
Input Function T3CKI to Input Pin Mapping Bits
---1 1111
RPINR4
Input Function T0CKI to Input Pin Mapping Bits
---1 1111
TABLE 6-4:
REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on Page:
Legend:
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note
1:
Bit 21 of the PC is only available in Serial Programming (SP) modes.
2:
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3:
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4:
Alternate names and definitions for these bits when the MSSP module is operating in I2C Slave mode. See Section 19.5.3.2 “Address
Masking Modes”
for details.
5:
These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
6:
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
7:
The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.
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