參數(shù)資料
型號(hào)： PIC18F45J50-I/ML
廠商： Microchip Technology
文件頁數(shù)： 114/164頁
文件大小： 0K
描述： IC PIC MCU FLASH 32K 2V 44-QFN
產(chǎn)品培訓(xùn)模塊： XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 45
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VQFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁面： 657 (CN2011-ZH PDF)
配用： AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2011 Microchip Technology Inc.
DS39931D-page 53
PIC18F46J50 FAMILY
FIGURE 4-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
4.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shutdown and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a wake
event, the CPU begins executing code being clocked by
the INTRC. The IDLEN and SCS bits are not affected by
the wake-up. The INTRC source will continue to run if
either the WDT or the FSCM is enabled.
4.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 4.2 “Run Modes”,
).
4.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
4.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is, when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed
mode
(see
and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 27.2 “Watchdog
).
The WDT and postscaler are cleared by one of the
following events:
Executing a SLEEP or CLRWDT instruction
The loss of a currently selected clock source (if
the FSCM is enabled)
4.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
OSC1
Peripheral
Program
PC
CPU Clock
Q1
Q3
Q4
Clock
Counter
Q2
Wake Event
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