PIC18F46J50 FAMILY
DS39931D-page 6
2011 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin QFN(1,3,4)
RA3
/AN3
/V
RE
F+/C1
INB
RA2
/AN2
/V
RE
F-/
C
V
RE
F
-/C
2
IN
B
RA1
/A
N
1
/C2
IN
A/
PM
A7
/RP
1
RA0
/AN0
/C1
IN
A/
UL
PWU/
PM
A6
/RP0
MC
L
R
RB7
/KBI
3
/PG
D/
RP1
0
RB
6/
K
B
I2
/P
GC/
RP
9
RB5
/PM
A0
/K
BI
1
/SDI
1/
S
DA
1
/RP8
R
B
4
/PM
A1
/K
B
I0
/SCK1
/S
CL
1/
RP7
NC
R
C
6/P
M
A
5/T
X
1/C
K
1/
RP1
7
RC5
/D+/
V
P
RC4
/D-
/VM
RD3
/PM
D
3/
RP2
0
RD2
/PM
D
2/
RP1
9
RD1
/P
M
D
1/
SDA2
RD0
/PM
D
0/
SCL
2
V
US
B
RC2
/AN1
1
/CT
P
L
S/
RP1
3
RC1/T
1O
S
I/UOE
/RP1
2
RC0
/T
1
O
SO/T
1C
KI/
RP1
1
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
AVDD
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/SS1/HLVDIN/RCV/RP2
VDDCORE/VCAP(2)
RC7/PMA4/RX1/DT1/SDO1/RP18
RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23
VSS
VDD
RB0/AN12/INT0/RP3
RB1/AN10/PMBE/RTCC/RP4
RB2/AN8/CTED1/PMA3/VMO/REFO/RP5
RB
3
/AN9
/C
T
ED2
/P
M
A2
/VPO
/RP
6
RD7/PMD7/RP24
AVSS
VDD
AVDD
Legend:
RPn
represents remappable pins.
Note
1:
Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be
dynamically assigned to any of the RPn pins. For a list of the input and output functions, see
Table 10-13.
2:
3:
For the QFN package, it is recommended that the bottom pad be connected to VSS.
4:
On 44-pin QFN devices, AVDD and AVSS reference sources are intended to be externally connected to VDD
and VSS levels. Other package types tie AVDD and AVSS to VDD and VSS internally.
= Pins are up to 5.5V tolerant
10
11
2
3
6
1
18
19
20 21 22
12 13
14 15
38
8
7
44
43
42 41
40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
5
4
PIC18F4XJ50