參數(shù)資料
型號: PIC16C56A-20I/JW
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18
封裝: 0.300 INCH, WINDOWED, CERDIP-18
文件頁數(shù): 90/158頁
文件大?。?/td> 1194K
代理商: PIC16C56A-20I/JW
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 37
PIC16C5X
7.4
Power-on Reset (POR)
The PIC16C5X family incorporates on-chip Power-on
Reset (POR) circuitry which provides an internal chip
RESET for most power-up situations. To use this fea-
ture, the user merely ties the MCLR/VPP pin to VDD. A
simplified block diagram of the on-chip Power-on Reset
circuit is shown in Figure 7-8.
The Power-on Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the Reset Latch is set and the DRT is
RESET. The DRT timer begins counting once it detects
MCLR to be high. After the time-out period, which is
typically 18 ms, it will reset the Reset Latch and thus
end the on-chip RESET signal.
A power-up example where MCLR is not tied to VDD is
shown in Figure 7-10. VDD is allowed to rise and stabi-
lize before bringing MCLR high. The chip will actually
come out of RESET TDRT msec after MCLR goes high.
In Figure 7-11, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together). The VDD
is stable before the start-up timer times out and there is
no problem in getting a proper RESET. However,
Figure 7-12 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses a high on the MCLR/VPP pin, and when the
MCLR/VPP pin (and VDD) actually reach their full value,
is too long. In this situation, when the start-up timer
times out, VDD has not reached the VDD (min) value and
the chip is, therefore, not guaranteed to function cor-
rectly. For such situations, we recommend that external
(RESET) BOR circuits or external RC circuits be used
to achieve longer POR delay times (Figure 7-9).
For more information on PIC16C5X POR, see
Power-Up Considerations - AN522 in the Embedded
Control Handbook.
The POR circuit does not produce an internal RESET
when VDD declines.
Note:
When the device starts normal operation
(exits the RESET condition), device oper-
ating parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in RESET until the
operating conditions are met.
FIGURE 7-9:
EXAMPLE OF EXTERNAL
POWER-ON RESET CIRCUIT
(FOR SLOW VDD POWER-UP)
C
R1
R
D
MCLR
PIC16C5X
VDD
External Power-on Reset circuit is required
only if VDD power-up is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
R < 40 k
is recommended to make sure that
voltage drop across R does not violate the
device electrical specification.
R1 = 100
to 1 k will limit any current flow-
ing into MCLR from external capacitor C in the
event of MCLR pin breakdown due to Electro-
static Discharge (ESD) or Electrical Over-
stress (EOS).
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