參數(shù)資料
型號(hào): PIC16C56A-20I/JW
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18
封裝: 0.300 INCH, WINDOWED, CERDIP-18
文件頁數(shù): 74/158頁
文件大?。?/td> 1194K
代理商: PIC16C56A-20I/JW
PIC16C5X
DS30453C-page 22
Preliminary
2000 Microchip Technology Inc.
FIGURE 4-9:
LOADING OF PC
BRANCH INSTRUCTIONS -
PIC16C57/PIC16CR57, AND
PIC16C58/PIC16CR58
4.5.1
PAGING CONSIDERATIONS –
PIC16C56/CR56, PIC16C57/CR57 AND
PIC16C58/CR58
If the Program Counter is pointing to the last address of
a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS Reg-
ister will not be updated. Therefore, the next GOTO,
CALL
or modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0 or
PA<1:0>).
For example, a NOP at location 1FFh (page 0) incre-
ments the PC to 200h (page 1). A GOTO xxx at 200h
will return the program to address 0xxh on page 0
(assuming that PA<1:0> are clear).
To prevent this, the page preselect bits must be
updated under program control.
4.5.2
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page (e.g., the RESET vector).
The STATUS Register page preselect bits are cleared
upon a RESET, which means that page 0 is
pre-selected.
Therefore, upon a RESET, a GOTO instruction at the
RESET vector location will automatically cause the pro-
gram to jump to page 0.
PA<1:0>
2
STATUS
PC
87
0
PCL
9
10
PA<1:0>
2
STATUS
PC
87
0
PCL
9
10
Instruction Word
Reset to ‘0’
Instruction Word
70
GOTO
Instruction
CALL
or Modify PCL Instruction
4.6
Stack
PIC16C5X devices have a 10-bit or 11-bit wide,
two-level hardware push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only the
most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW
’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W Register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the pro-
gram memory.
For the RETLW instruction, the PC is loaded with the
Top of Stack (TOS) contents. All of the devices covered
in this data sheet have a two-level stack. The stack has
the same bit width as the device PC.
4.7
Indirect Data Addressing; INDF and
FSR Registers
The INDF Register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR Register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 4-1:
INDIRECT ADDRESSING
Register file 08 contains the value 10h
Register file 09 contains the value 0Ah
Load the value 08 into the FSR Register
A read of the INDF Register will return the value
of 10h
Increment the value of the FSR Register by one
(FSR = 09h)
A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF Register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw
0x10
;initialize pointer
movwf
FSR
; to RAM
NEXT
clrf
INDF
;clear INDF Register
incf
FSR,F
;inc pointer
btfsc
FSR,4
;all done?
goto
NEXT
;NO, clear next
CONTINUE
:
;YES, continue
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