參數(shù)資料
型號: PIC12F519
廠商: Microchip Technology Inc.
英文描述: 8-Pin, 8-Bit Flash Microcontroller
中文描述: 8引腳,8位閃存微控制器
文件頁數(shù): 65/88頁
文件大?。?/td> 802K
代理商: PIC12F519
2007 Microchip Technology Inc.
Preliminary
DS41319A-page 63
PIC12F519
11.1
DC CHARACTERISTICS: PIC12F519 (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 40
°
C
T
A
+85
°
C (industrial)
Param
No.
Sym
Characteristic
Min
Typ
(1)
Max
Units
Conditions
D001
D002
D003
V
DD
V
DR
V
POR
Supply Voltage
RAM Data Retention Voltage
(2)
V
DD
Start Voltage
to ensure
Power-on Reset
V
DD
Rise Rate
to ensure
Power-on Reset
2.0
5.5
V
V
V
See
Figure 11-1
Device in Sleep mode
See
Section 8.4 “Power-on
Reset (POR)”
for details
See
Section 8.4 “Power-on
Reset (POR)”
for details
(Note 6)
F
OSC
= 4 MHz, V
DD
= 2.0V
F
OSC
= 4 MHz, V
DD
= 5.0V
F
OSC
= 8 MHz, V
DD
= 2.0V
F
OSC
= 8 MHz, V
DD
= 5.0V
F
OSC
= 32 kHz, V
DD
= 2.0V
F
OSC
= 32 kHz, V
DD
= 5.0V
V
DD
= 2.0V
V
DD
= 5.0V
V
DD
= 2.0V
V
DD
= 5.0V
1.5*
Vss
D004
S
VDD
0.05*
V/ms
D010
I
DD
Supply Current
(3,4)
175
0.625
250
1.0
11
38
0.1
0.35
1.0
7.0
275
1.1
450
1.5
15
52
1.2
2.2
3.0
16.0
μ
A
mA
μ
A
mA
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
D020
I
PD
Power-down Current
(5)
D022
I
WDT
WDT Current
(5)
*
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is based on characterization results at 25
°
C. This data is for design
guidance only and is not tested.
This is the limit to which V
DD
can be lowered in Sleep mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
The test conditions for all I
DD
measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V
SS
, T0CKI = V
DD
, MCLR =
V
DD
; WDT enabled/disabled as specified.
For standby current measurements, the conditions are the same as I
DD
, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
This rise rate applies if the clock mode selected (LP, XT) allows DRT to hold the device in Reset within
18 ms (nominal delay) DRT. Otherwise, the user must ensure that V
DD
reaches V
DDMIN
before DRT
expires.
Note 1:
2:
3:
4:
5:
6:
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