參數(shù)資料
型號: PIC12F519
廠商: Microchip Technology Inc.
英文描述: 8-Pin, 8-Bit Flash Microcontroller
中文描述: 8引腳,8位閃存微控制器
文件頁數(shù): 46/88頁
文件大?。?/td> 802K
代理商: PIC12F519
PIC12F519
DS41319A-page 44
Preliminary
2007 Microchip Technology Inc.
8.5
Device Reset Timer (DRT)
On the PIC12F519 device, the DRT runs any time the
device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
Table 8-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows V
DD
to rise above V
DD
min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the devices in
a Reset condition after MCLR has reached a logic high
(V
IH
MCLR) level. Programming RB3/MCLR/V
PP
as
MCLR and using an external RC network connected to
the MCLR input is not required in most cases. This
allows savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the
RB3/MCLR/V
PP
pin as a general purpose input.
The Device Reset Time delays will vary from
chip-to-chip due to V
DD
, temperature and process vari-
ation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See
Section 8.8.2 “Wake-up
from Sleep”, Notes 1, 2 and 3
.
TABLE 8-5:
DRT (DEVICE RESET TIMER
PERIOD)
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (RB5)/OSC1/CLKIN pin
and the internal 4 or 8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a
SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘
0
’ (see
Section 8.1
“Configuration Bits”
). Refer to the PIC12F519 Pro-
gramming Specifications to determine how to access
the Configuration Word.
8.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These peri-
ods vary with temperature, V
DD
and part-to-part pro-
cess variations (see DC specs).
Under worst-case conditions (V
DD
= Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING
CONSIDERATIONS
The
CLRWDT
instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The
SLEEP
instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Oscillator
Configuration
POR Reset
Subsequent
Resets
INTOSC, EXTRC
1 ms (typical)
10
μ
s (typical)
LP, XT
18 ms (typical)
18 ms (typical)
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