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參數(shù)資料
| 型號(hào)： | PI7C7100CNA |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3-Port PCI Bridge |
| 中文描述： | 3端口PCI橋 |
| 文件頁(yè)數(shù)： | 44/132頁(yè) |
| 文件大?。?/td> | 2559K |
| 代理商： | PI7C7100CNA |
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09/18/00 Rev 1.1
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7.2.2 Read Transactions
When PI7C7100 detects a parity error during a read transaction, the target drives data and data parity, and the initiator
checks parity and conditionally asserts PERR#.
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
For downstream transactions, when PI7C7100 detects a read data parity error on the secondary bus, the following events
occur:
PI7C7100 asserts S_PERR# two cycles following the data transfer, if the secondary interface parity error re-
sponse bit is set in the bridge control register.
PI7C7100 sets the detected parity error bit in the secondary status register.
PI7C7100 sets the data parity detected bit in the secondary status register, if the secondary interface parity error
response bit is set in the bridge control register.
PI7C7100 forwards the bad parity with the data back to the initiator on the primary bus.
If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is
discarded and the data with bad parity is not returned to the initiator.
PI7C7100 completes the transaction normally.
For upstream transactions, when PI7C7100 detects a read data parity error on the primary bus, the following events occur:
PI7C7100 asserts P_PERR# two cycles following the data transfer, if the primary interface parity error
response bit is set in the command register.
PI7C7100 sets the detected parity error bit in the primary status register.
PI7C7100 sets the data parity detected bit in the primary status register, if the primary interface parity-error-
response bit is set in the command register.
PI7C7100 forwards the bad parity with the data back to the initiator on the secondary bus.
If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is
discarded and the data with bad parity is not returned to the initiator.
PI7C7100 completes the transaction normally.
PI7C7100 returns to the initiator the data and parity that was received from the target. When the initiator detects
a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data
transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore,
when PI7C7100 detects PERR# asserted while returning read data to the initiator, PI7C7100 does not take any
further action and completes the transaction normally.
7.2.3 Delayed Write Transactions
When PI7C7100 detects a data parity error during a delayed write transaction, the initiator drives data and data parity,
and the target checks parity and conditionally asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C7100 completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits,
and data parity are all captured and a target retry is returned to the initiator. When PI7C7100 detects a parity error on
the write data for the initial delayed write request transaction, the following events occur:
If the parity-error-response bit corresponding to the initiator bus is set, PI7C7100 asserts TRDY# to the initiator
and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a
target disconnect. Two cycles after the data transfer, PI7C7100 also asserts PERR#.
If the parity-error-response bit is not set, PI7C7100 returns a target retry. It queues the transaction as usual.
PI7C7100 does not assert PERR#. In this case, the initiator repeats the transaction.
PI7C7100 sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless
of the state of the parity-error-response bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
| PI7C8140A | 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8148B | 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300ANAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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