參數(shù)資料
型號(hào)： PHW7N60
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： JFETs
英文描述： PowerMOS transistor
中文描述： 7 A, 600 V, 1.2 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247
封裝： PLASTIC PACKAGE-3
文件頁(yè)數(shù)： 1/7頁(yè)
文件大小： 56K
代理商： PHW7N60
Philips Semiconductors
Product specification
PowerMOS transistor
PHW7N60
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
field-effect power transistor in a
plastic
envelope
avalanche energy capability, stable
off-state
characteristics,
switching and high thermal cycling
performance
with
resistance.
Intended
Switched
Mode
(SMPS), motor control circuits and
general
purpose
applications.
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
featuring
high
V
DS
I
D
P
tot
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
600
7
147
1.2
V
A
W
fast
low
for
thermal
use
Supplies
in
Power
switching
PINNING - SOT429 (TO247)
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
Continuous drain current
CONDITIONS
T
mb
= 25 C; V
GS
= 10 V
T
mb
= 100 C; V
GS
= 10 V
T
mb
= 25 C
T
mb
= 25 C
T
mb
> 25 C
MIN.
-
-
-
-
-
-
-
MAX.
7
4.5
28
147
1.176
±
30
570
UNIT
A
A
A
W
W/K
V
mJ
I
DM
P
D
P
D
/
T
mb
Linear derating factor
V
GS
Gate-source voltage
E
AS
Single pulse avalanche
energy
I
AS
Peak avalanche current
Pulsed drain current
Total dissipation
V
DD
≤
50 V; starting T
j
= 25C; R
GS
= 50
;
V
GS
= 10 V
V
DD
≤
50 V; starting T
j
= 25C; R
GS
= 50
;
V
GS
= 10 V
-
7
A
T
j
, T
stg
Operating junction and
storage temperature range
- 55
150
C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN.
-
TYP.
-
MAX.
0.85
UNIT
K/W
R
th j-a
-
45
-
K/W
2
3
1
d
g
s
June 1997
1
Rev 1.000
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