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參數(shù)資料
| 型號： | PHU2N50E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | PowerMOS transistors Avalanche energy rated |
| 中文描述： | 2 A, 500 V, 5 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-251 |
| 封裝： | PLASTIC, IPAK-3 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 64K |
| 代理商： | PHU2N50E |
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHU2N50E
FEATURES
QUICK REFERENCE DATA
Repetitive Avalanche Rated
Fast switching
Stable off-state characteristics
High thermal cycling performance
Low thermal resistance
Extremely high dV/dt capability
V
DSS
= 500 V
I
D
= 2 A
R
DS(ON)
≤
5
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, intended for use in
C
ompact
F
luorescent
L
amps (CFL)
andlowpowerballasts.ThePHU2N50EiscompatiblewithselfoscillatingandICdrivencircuits,including theUBA2021
ballast controller IC. Other applications include off line switched mode power supplies and D.C. to D.C. converters.
The PHU2N50E is supplied in the SOT533 (I-PAK) leaded package.
PINNING
SYMBOL
SOT533
PIN
DESCRIPTION
------------- ---------------------------------
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage
I
D
Continuous drain current
CONDITIONS
T
j
= 25 C to 150C
T
j
= 25 C to 150C; R
GS
= 20 k
MIN.
-
-
-
-
-
-
-
-
MAX.
500
500
±
30
2
1.3
8
50
5.2
UNIT
V
V
V
A
A
A
W
V/ns
T
mb
= 25 C; V
GS
= 10 V
T
mb
= 100 C; V
GS
= 10 V
T
mb
= 25 C
T
mb
= 25 C
I
ds
2.0 A; dI/dt = 100 A/
μ
s;
V
s
= 8V; T
j
< T
jmax
I
DM
P
dV/dt
Pulsed drain current
Total dissipation
Peak Diode Recovery
voltage slope. (See fig. 19)
Operating junction and
storage temperature range
T
j
, T
stg
- 55
150
C
d
g
s
1
Top view
MBK915
2
3
May 1999
1
Rev 1.000
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