參數(shù)資料
型號(hào): PHT6N03LT
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: TrenchMOS transistor Logic level FET
中文描述: 5.9 A, 30 V, 0.03 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝: SOT-223, 4 PIN
文件頁數(shù): 1/6頁
文件大?。?/td> 53K
代理商: PHT6N03LT
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
PHT6N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 30 V
’Trench’
technology
Very low on-state resistance
Fast switching
Stable off-state characteristics
High thermal cycling performance
Surface mounting package
I
D
= 5.9 A
R
DS(ON)
30 m
(V
GS
= 5 V)
R
DS(ON)
28 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
PINNING
SOT223
N-channel
logic
transistor
technology. The device has very
low
on-state
resistance.
intended for use in dc to dc
converters and general purpose
switching applications.
enhancement
field-effect
using
mode
power
trench
PIN
DESCRIPTION
level
1
gate
It
is
2
drain
3
source
tab
drain
The PHT6N03LT is supplied in the
SOT223
surface
package.
mounting
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage
I
D
Continuous drain current
CONDITIONS
T
j
= 25 C to 150C
T
j
= 25 C to 150C; R
GS
= 20 k
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
±
13
5.9
4.1
23.6
1.8
150
UNIT
V
V
V
A
A
A
W
C
T
amb
= 25 C; V
GS
= 10 V
T
amb
= 100 C; V
GS
= 10 V
I
DM
P
D
T
j
, T
stg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T
amb
= 25 C
ESD LIMITING VALUE
SYMBOL PARAMETER
V
C
Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
Human body model (100 pF, 1.5 k
)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-sp
Thermal resistance junction
to solder point
R
th j-a
Thermal resistance junction
to ambient
CONDITIONS
mounted on any pcb
MIN.
-
TYP. MAX. UNIT
-
15
K/W
mounted on test pcb of fig:17
-
70
-
K/W
d
g
s
4
1
2
3
January 1998
1
Rev 1.300
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