參數(shù)資料
型號(hào): PHB130N03LT
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: TrenchMOS transistor Logic level FET
中文描述: 75 A, 30 V, 0.006 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝: PLASTIC, SOT-404, 3 PIN
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 63K
代理商: PHB130N03LT
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
PHB130N03LT
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting using ’
trench
’ technology.
Thedevicefeaturesverylowon-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in DC-DC
converters and
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
V
DS
I
D
P
tot
T
j
R
DS(ON)
Drain-source voltage
Drain current (DC)
1
Total power dissipation
Junction temperature
Drain-source on-state
resistance
30
75
187
175
6
V
A
W
C
m
V
GS
= 5 V
general purpose
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
mb
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
1
Drain current (DC)
1
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
10
75
75
240
187
175
UNIT
V
V
V
A
A
A
W
C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
TYP.
-
MAX.
0.8
UNIT
K/W
R
th j-a
minimum footprint, FR4
board
50
-
K/W
d
g
s
1
3
mb
2
1
Current limited by package to 75A from a theoretical value of 130A.
December 1997
1
Rev 1.200
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