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| 型號： | PEDL9352-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 128-Channel Organic EL Driver with Built-in RAM |
| 中文描述： | 128通道有機(jī)EL帶內(nèi)置驅(qū)動器在RAM |
| 文件頁數(shù)： | 53/53頁 |
| 文件大?。?/td> | 302K |
| 代理商： | PEDL9352-01 |
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PEDL9352-01
OKI Semiconductor
ML9352
9/53
Display data RAM
Display data RAM
This is the RAM storing the dot data for display and has an organization of 32
× 128 bits. It is possible to access
any required bit by specifying the write address and the column address. Since the display data D7 to D0 from the
MPU corresponds to the organic EL display in the direction of the common lines as shown in Figure 3. Also, since
the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the
signal read operation for the organic EL drive. Consequently, the display is not affected by flickering, etc., even
when the display data RAM is accessed asynchronously during the organic EL display operation.
D0
0 1 1 1 - - - 0
D1
1 0 0 0 - - - 0
D2
0 0 0 0 - - - 0
D3
0 1 1 1 - - - 0
D4
1 0 0 0 - - - 0
Display data RAM
COM0
- - -
COM1
- - -
COM2
- - -
COM3
- - -
COM4
- - -
Organic EL Display
Figure 3
Write address circuit
The write address of the display data RAM is specified using the write address set command as shown in Figures
4-1 to 4-10. Write display data in units of 8 bits in the direction of the common lines, starting at the specified write
address.
Column address circuit
The column address of the display data RAM is specified using the column address set command as shown in
Figures 4-1 to 4-10. Since the specified column address is incremented (by +1) every time a display data
read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the
column address is stopped at the column address of 7FH. Since the column address and the write address are
independent of each other, it is necessary, for example, to specify separately the new write address and the new
column address when changing from column 7FH of write address 07H to column 00H of write address 08H. Also,
as is shown in Table 4, it is possible to reverse the correspondence relationship between the display data RAM
column address and the SEG output using the ADC command (the anode driver direction select command). This
reduces the IC placement restrictions at the time of assembling organic EL modules.
Table 4
ADC
SEG Output
SEG0
SEG127
D0 = “0”
0(H)
→ Column Address → 7F(H)
D0 = “1”
7F(H)
← Column Address ← 0(H)
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