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參數(shù)資料
| 型號(hào)： | PEDL9352-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 128-Channel Organic EL Driver with Built-in RAM |
| 中文描述： | 128通道有機(jī)EL帶內(nèi)置驅(qū)動(dòng)器在RAM |
| 文件頁數(shù)： | 52/53頁 |
| 文件大?。?/td> | 302K |
| 代理商： | PEDL9352-01 |
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PEDL9352-01
OKI Semiconductor
ML9352
8/53
Data write
DATA
BUS Holder
N
Latch
N+1
N+2
N+3
N
N+1
N+2
N+3
WR
MP
U
Write Signal
Intern
al
t
imi
ng
Figure 2(a)
Data read
DATA
Column
Address
Read Signal
Address
Preset
N
n
n+1
Preset N
N
n
n+1
n+2
Increment N+1
N+2
RD
MP
U
WR
BUS Holder
Intern
al
t
imi
ng
Address Set
#n
Dummy
Read
Data Read
#n
Data Read
#n+1
Figure 2(b)
Busy flag
The busy flag being “1” indicates that the ML9352 is carrying out internal operations, and hence no instruction
other than a status read instruction is accepted during this period. The busy flag is output at pin D7 when a status
read instruction is executed. If the cycle time (tCYC) is established, there is no need to check this flag before issuing
every command and hence the processing performance of the MPU can be increased greatly.
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