參數(shù)資料
型號(hào)： PCX7447AVGH1000NB
廠商： Atmel
文件頁(yè)數(shù)： 45/52頁(yè)
文件大小： 0K
描述： IC MPU 32BIT 1000MHZ 360CBGA
標(biāo)準(zhǔn)包裝： 44
處理器類型： PowerPC 32-位 RISC
速度： 1.0GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 360-CBBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 360-CBGA（25x25）
包裝： 托盤(pán)
5
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
Rename buffers
– 16 GPR rename buffers
– 16 FPR rename buffers
– 16 VR rename buffers
Dispatch unit
– Decode/dispatch stage fully decodes each instruction
Completion unit
– The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending
– Guarantees sequential programming model (precise exception model)
– Monitors all dispatched instructions and retires them in order
– Tracks unresolved branches and flushes instructions after a mispredicted branch
– Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard Architecture)
– 32-Kbyte, eight-way set-associative instruction and data caches
– Pseudo least-recently-used (PLRU) replacement algorithm
– 32-byte (eight-word) L1 cache block
– Physically indexed/physical tags
– Cache write-back or write-through operation programmable on a per-page or per-block basis
– Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
– Caches can be disabled in software
– Caches can be locked in software
– MESI data cache coherency maintained in hardware
– Separate copy of data cache tags for efficient snooping
– Parity support on cache and tags
– No snooping of instruction cache except for icbi instruction
– Data cache supports AltiVec LRU and transient instructions
– Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
– On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache
– Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
– A total nine-cycle load latency for an L1 data cache miss that hits in L2
– Cache write-back or write-through operation programmable on a per-page or per-block basis
64-byte, two-sectored line size
– Parity support on cache
Separate memory management units (MMUs) for instructions and data
– 52-bit virtual address, 32- or 36-bit physical address
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCX7447AVGH1167NB 功能描述:IC MPU 32BIT 1167MHZ 360CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤(pán)
PCX7448MGH1000NC 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays
PCX7448MGH1250NC 制造商:e2v technologies 功能描述:PCX7448MGH1250NC - Trays
PCX7448VGH1000NC 制造商:e2v technologies 功能描述:PCX7448VGH1000NC - Trays
PCX7448VGH1250NC 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays
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