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| 型號： | PCX7447AVGH1000NB |
| 廠商： | Atmel |
| 文件頁數(shù)： | 19/52頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 1000MHZ 360CBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 處理器類型： | PowerPC 32-位 RISC |
| 速度： | 1.0GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 360-CBGA（25x25） |
| 包裝： | 托盤 |
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26
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre-
quency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section “PLL Configuration” on page 38 for valid
PLL_CFG[0:4] settings.
2. Assumes a lightly-loaded, single-processor system.
3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V.
4. Timing is guaranteed by design and characterization.
5. Guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at -3 dB.
7. Relock timing is guaranteed by design and characterization. PLL relock time is the maximum amount of time required for
PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.
8. Caution: If DFS is enabled, the SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting pro-
cessor frequency is greater than or equal to the minimum core frequency.
9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at the nomi-
nal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies must be
reduced.
Figure 9-1 provides the SYSCLK input timing diagram.
Figure 9-1.
SYSCLK Input Timing Diagram
V
M = Midpoint Voltage (OVDD/2)
Symbol
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000 MHz
1167 MHz
VDD = 1.1V
Min
Max
Min
Max
fCORE
Processor core frequency
500
1000
500
1167
MHz
fVCO
VCO frequency
1000
2000
1000
2233
MHz
f
SYSCLK
SYSCLK frequency
33
167
33
167
MHz
tSYSCLK
SYSCLK cycle time
6
30
6
30
ns
tKR, tKF
SYSCLK rise and fall time
–
1
–
1
ns
t
KHKL/tSYSCLK
SYSCLK duty cycle measured at OV
DD/2
40
60
40
60
%
SYSCLK jitter(5)(6)
–150–150
ps
Internal PLL relock time(7)
–100–100
s
SYSCLK
VM
tKHKL
tSYSCLK
CVIL
CVIH
tKR
tKF
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| PCX7447AVGH1167NB | 功能描述:IC MPU 32BIT 1167MHZ 360CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| PCX7448MGH1000NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
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| PCX7448VGH1000NC | 制造商:e2v technologies 功能描述:PCX7448VGH1000NC - Trays |
| PCX7448VGH1250NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
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