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參數(shù)資料
| 型號： | PCM1740 |
| 英文描述： | CONN,CPRSN,2-WAY |
| 中文描述： | 立體聲音頻數(shù)模轉(zhuǎn)換器與石英振蕩器和PLL |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 359K |
| 代理商： | PCM1740 |
9
PCM1740
The PLL can generate one of nine pre-programmed system
clock rates for either 256f
S
or 384f
S
output. The PLL output
and sampling frequencies are programmed using Control
Register 3. Table I shows the available sampling frequencies
and the corresponding PLL output clock rates. The reset
default condition for the PLL is f
S
= 44.1kHz with SCKO =
384f
S
, or 16.9344MHz.
At power up, the PLL requires 30ms start up time for
stabilization. The PLL also exhibits a settling time of 20ms
in response to changes in sampling frequency selection.
The PLL output continues to operate during power on or
external reset sequences, with the sampling frequency set to
f
S
= 44.1kHz and SCKO = 384f
S
.
RESET OPERATION
POWER ON RESET
The PCM1740 includes power-on reset circuitry for start up
initialization. The initialization sequence starts when V
DD
exceeds 2.2V (typical). The initialization sequence requires
1024 PLL output (or SCKO) clock cycles for completion.
During initialization, both V
OUT
L and V
OUT
R are forced to
V
CC
/2. Figure 6 shows the power on reset timing, while
Table II shows the reset default settings for user-program-
mable functions. The user should not attempt to write
control registers via the I
2
C-Bus interface during the initial-
ization sequence.
EXTERNAL RESET
The PCM1740 includes an external reset input, RST (pin
10). This input may be used to force an initialization se-
quence. As shown in Figure 7, the RST pin must be held low
for a minimum of 20ns. The initialization sequence will then
start on the rising edge of RST. Initialization requires 1024
PLL output (or SCKO) clock cycles for completion. During
initialization, both V
OUT
L and V
OUT
R are forced to V
CC
/2.
Table II shows the reset default settings for user-program-
mable functions. The user should not attempt to write
control registers via the I
2
C-Bus interface during the initial-
ization sequence.
SAMPLING
FREQUENCY (LRCK)
INTERNAL SYSTEM
Clock - 256f
S
INTERNAL SYSTEM
Clock - 384f
S
16kHz
32kHz
64kHz
22.05kHz
44.1kHz
88.2kHz
24kHz
48kHz
96kHz
Half
Normal
Double
Half
Normal
Double
Half
Normal
Double
4.096MHz
8.192MHz
16.384MHz
5.6448MHz
11.2896MHz
22.5792MHz
6.144MHz
12.288MHz
24.576MHz
6.144MHz
12.288MHz
24.576MHz
8.4672MHz
16.9344MHz
33.8688MHz
9.216MHz
18.432MHz
36.864MHz
TABLE I. PLL Sampling and System Clock Frequencies.
1024 System Clock Periods
Reset
Reset Removal
2.4V
2.2V
2.0V
V
CC
/V
DD
Internal Reset
System Clock
(SCKO)
1024 System Clock Periods
Reset
Reset Removal
System Clock
(SCKO)
Internal Reset
RST
t
RST
t
RST
t
RST
≥
20ns
FIGURE 6. Power-On Reset Operation.
FIGURE 7. External Reset Operation.
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| PCM1740E | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1740E/2K | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1740E/2KG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1740E-1/2K | 制造商:Texas Instruments 功能描述: |
| PCM1740EG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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