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參數(shù)資料
| 型號： | PCM1740 |
| 英文描述： | CONN,CPRSN,2-WAY |
| 中文描述： | 立體聲音頻數(shù)模轉(zhuǎn)換器與石英振蕩器和PLL |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 359K |
| 代理商： | PCM1740 |
16
PCM1740
Data transfer begins with a Start condition, and is immedi-
ately followed by the Slave address and Read/Write bit. The
Read/Write bit is set to “0” for the PCM1740, in order to
write data to the control register specified by the sub-
address. This is followed by an acknowledgment from the
PCM1740, the sub-address (i.e., control register address),
another acknowledgment from the PCM1740, the control
register data, and another acknowledgment from the
PCM1740. What happens after this depends upon if the user
wants to continue writing additional control registers, or if
they want to terminate the data transfer. If the user wants to
continue, the acknowledgment is followed by a Start condi-
tion for the next write sequence. If the user decides to
terminate the data transfer, then a Stop condition is gener-
ated by the Master.
The I
2
C-Bus specification defines timing requirements for
devices connected to the bus. Timing requirements for the
PCM1740 are shown in Figure 15.
Reference
For additional information regarding the I
2
C-Bus, please
refer to the I
2
C-Bus Specification, Version 2.0, published in
December 1998 by Philips Semiconductors.
FIGURE 15. I
2
C Bus Timing.
SDA
SCL
S: START condition
Sr: repeated START condition
P: STOP condition
t
F
t
HD; STA
S
Sr
P
S
t
HD; DAT
t
HIGH
t
SU; STA
t
SU; STO
t
R
t
HD; STA
t
R
t
LOW
t
F
t
SU, DAT
t
BUF
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
f
SCL
t
HD; STA
SCL Clock Frequency
Hold time (repeated) START condition,
after this period, the first clock pulse is
generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time for I
2
C-BUS devices
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Noise margin at the LOW level for each
connected device (including hysteresis)
Noise margin at the HIGH level for each
connected device (including hysteresis)
100
kHz
μ
s
4.0
t
LOW
t
HIGH
t
SU:STA
t
HD;DAT
t
SU;DAT
t
R
t
F
t
SU;STO
t
BUF
4.7
4.0
4.7
0
250
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
μ
s
3.45(2)
1000
300
4.0
4.7
C
B
V
NL
400
pF
V
0.1 V
DD
V
NH
0.2 V
DD
V
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| PCM1740E/2KG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1740E-1/2K | 制造商:Texas Instruments 功能描述: |
| PCM1740EG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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