參數(shù)資料
型號: PCM1740
英文描述: CONN,CPRSN,2-WAY
中文描述: 立體聲音頻數(shù)模轉(zhuǎn)換器與石英振蕩器和PLL
文件頁數(shù): 15/20頁
文件大?。?/td> 359K
代理商: PCM1740
15
PCM1740
I
2
C-BUS INTERFACE DESCRIPTION
The PCM1740 includes an I
2
C-Bus interface for writing the
internal control registers. This provides an industry standard
method for interfacing a host CPU control port to the
PCM1740. The PCM1740 operates as a Slave receiver on
the bus, and supports data transfer rates up to 100 kilobits-
per-second (kbps).
The I
2
C-Bus interface is comprised of four signals: SDA
(pin 9), SCL (pin 8), AD0 (pin 6), and AD1 (pin 7). The SCL
input is the serial data clock, while SDA is the serial data
input. SDA carries start/stop, slave address, sub-address (or
register address), register, and acknowledgment data. The
AD0 and AD1 inputs form the lower two bits of the slave
address.
Slave Address
The PCM1740 Slave address consists of seven bits, as shown
in Figure 12. The five most significant bits are fixed, while the
two least significant bits, named A0 and A1, are defined by the
logic levels present at the AD0 and AD1 input pins. This
allows four PCM1740’s to reside on the same I
2
C-Bus.
Bus Operation
Figure 13 shows the typical configuration of the PCM1740 on
the I
2
C-Bus. The Master transmitter or transmitter/receiver is
typically a microcontroller, or an audio DSP/decoder. The
Master device controls the data transfers on the bus. The
PCM1740 operates as a Slave receiver, and accepts data from
the Master when it is properly addressed. The data transfer
may be comprised of an unlimited number of bytes, or 8-bit
data words. Figure 14 shows the message transfer protocol.
For normal bit transfer on the bus, data on SDA must
be static while SCL is High. Data on SDA may change
High/Low states when SCL is Low. The exception to this
rule is the Start and Stop conditions.
The Start condition is defined by a High-to-Low transition on
SDA while SCL is High, and is denoted with an “S” in Figure
12. The Stop condition is defined by a Low-to-High transition
on SDA while SCL is High, and is denoted with a “P” in
Figure 12. The Start and Stop conditions are always generated
by the Master. All data transfers from Master to Slave begin
with a Start condition and end with a Stop condition. The bus
is considered to be busy after the Start condition, and becomes
free some time after the Stop condition.
Master
Transmitter/
Receiver
SCL
SDA
Slave
Receiver
(PCM1740)
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
SDA
SCL
Start
Condition
Start
Condition
Stop
Address
Address
R/W
R/W
ACK
ACK
ACK
Data
1-7
1-7
8
8
9
9
9
8
1-7
NOTES: (1) Clock LOW (min) = 4.7
μ
s; clock HIGH (min) = 4
μ
s. (2) The dased line is the
acknoweledgement of the receiver. (3) Mark-to space ratio = 1:1 (LOW-to-HIGH). (4) Maximum
number of bytes is unrestriced. (5) Premature termination of transfer is allowed by generation of
STOP condition. (6) Acknowledge clock bit must be provided by master.
FIGURE 12. Control Data Format.
FIGURE 13. Typical I
2
C-Bus Configuration.
FIGURE 14. I
2
C Bus Data Transfer.
0
1
Slave Address
1
A1 A0
S
1
0
0
MSB
R/W
A
B12 B11B10
B15B14 B13
B09B08 A B07 B06
B02 B01B00
B05 B04 B03
A
Internal Strobe for
Data Latching
Not Acknowledge
P
Acknowledge
from
Slave
Acknowledge
from
Slave
Start
from
Master
Stop
from
Master
Sub Address Byte
Data Byte
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