參數(shù)資料
型號(hào)： PCF26100ET
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： DVI_D - DVI_D SINGLE LINK CABLE 5M BLK RoHS Compliant: Yes
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA48
封裝： 5 X 5 X 0.80 MM, PLASTIC, TFBGA-48
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 121K
代理商： PCF26100ET
2001 Jun 19
10
Philips Semiconductors
Preliminary specification
Bluetooth Adapter IC
PCF26100
Table 3
Adapter timing parameters
PARAMETER
DESCRIPTION
VALUE
UNIT
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
SYNTH_ON rising edge to 3-wire serial data
SYNTH_ON rising edge to REFCLK start
S_EN falling edge to REFCLK stop delay
S_EN falling edge to RSSI measurement
SYNTH_ON rising edge to S_EN rising edge
S_EN width
SYNTH_ON falling edge to S_EN pulse rising edge
SYNTH_ON falling edge to S_EN pulse rising edge
S_EN pulse width
SYNTH_ON rising edge to T_GFSK DC bias and TXCLK
enable
TX_DATA digital in to T_GFSK analog out delay
S_EN pulse falling edge to T_GFSK LOW and TXCLK
disable
S_EN falling edge to SLCCTR rising edge
PX_ON rising edge to SLCCTR falling edge
SYNTH_ON rising edge to T_SW rising edge
S_EN pulse falling edge to T_SW falling edge
0.35
S_EN start
2
RSSI_start
S_EN start
S_EN width
S_EN pulse start
S_EN pulse start
2
GFSK_DC_bias start
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
t
11
t
12
14
0
13 MHz cycles
μ
s
t
13
t
14
t
17
t
18
SLCCTR start
0
T_SW start
0
μ
s
μ
s
μ
s
μ
s
6.3.1
T_GFSK
The T_GFSK data output has 3 phases:
1.
Idle phase
2.
DCbias phase
3.
Txdata phase.
The Idle phase is used outside transmit packets. In this
phase the T_GFSK output state is defined by the
‘gfsk float’ bit in the Enable Register. If the ‘gfsk float’ bit is
set to a logic 0, the T_GFSK output is pulled to ground; if
set to a logic 1 the T_GFSK output is floating.
The DCbias phase is used during the transmit slot as
start-up phase before the transmit data. The DCbias
phase is active GFSK_DC_BIAS_Start delay following the
S_EN rising edge until the first transmit data bit on
TX_DATA.
During this phase a DC bias is generated by the GFSK
filter, which is achieved by selecting the GFSK table
mid-value as the output of the GFSK filter.
The Txdata phase is used when TXDATA is present.
In this phase the TX_DATA is fed into the GFSK filter. The
presence of TXDATA is determined by detecting the first
TXDATA edge. The end of the TXDATA is detected by the
end of packet from the baseband controller. To not lose
TXDATA information in the T_GFSK output, due to the
data detection, the data from the GFSK input is delayed
with 1-bit.
The T_GFSK output requires an external low-pass filter.
ThereferencevoltagefortheT_GFSKcomesdirectlyfrom
the V
DDA
power supply. Any variation on V
DDA
has a direct
relation to a variation in the T_GFSK levels. The V
DDA
power supply should be provided from a voltage reference.
The TX_CLK output is activated during the DC_BIAS
phase and the Txdata phase.
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