參數(shù)資料
型號： PCD5008H
廠商： NXP SEMICONDUCTORS
元件分類： 尋呼電路
英文描述： FLEX Pager Decoder
中文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁數(shù)： 20/64頁
文件大?。?/td> 341K
代理商： PCD5008H
1998 Jun 17
20
Philips Semiconductors
Product specification
FLEX
Pager Decoder
PCD5008
8.4.9
S
TATUS PACKET
(ID = 7FH)
The status packet contains various types of information
that the host may require and is sent to the host:
Whenever the PCD5008 is polled and has no other data
to send
On events for which the PCD5008 is configured to send
the status packet (Sections 8.4.4 and 8.4.7). In this
case, the PCD5008 prompts the host to read a status
packet for the following conditions:
– SMU bit in the status packet and the SME bit in the
configuration packet are set
– MT bit in the status packet and the MTE bit in the
configuration packet are set
– EOF bit in the status packet is set
– LBU bit in the status packet is set
– BOE bit in the status packet is set.
FIV:
frame information valid (Table 12). This bit is set,
when a valid frame information word has been received
since becoming synchronous to the system and the
f and c fields contain valid values. If this bit is clear, no
valid frame information words have been received since
the PCD5008 became synchronous to the system. This
value changes from 0 to 1 at the end of block 0 (Fig.17) of
the frame in which the first frame information word was
properly received. It is cleared when the PCD5008 goes
into asynchronous mode (see SM bit below). This bit is
initialized to 0 when the PCD5008 is reset and when the
PCD5008 is turned off by clearing the ON bit in the control
packet.
f:
current frame number (Table 12). This value is updated
every frame regardless of whether the PCD5008 needs to
decode the frame. This value changes to its proper value
for a frame at the end of block 0 of the frame. The value of
these bits is not guaranteed when FIV is 0.
c:
current system cycle number (Table 12). This value is
updated every frame regardless of whether the PCD5008
needs to decode the frame. This value changes to its
proper value for a frame at the end of block 0 of the frame.
The value of these bits is not guaranteed when FIV is 0.
SM:
synchronous mode (Table 12). This bit is set, when
the PCD5008 is synchronous to the system.
The PCD5008 sets this bit when the first synchronization
words are received. It clears this bit when synchronisation
to the FLEX
signal is lost. This bit is initialized to 0 when
the PCD5008 is reset and when it is turned off by clearing
the ON bit in the control packet.
SMU:
synchronous mode update (Table 12). This bit is set
if the SM bit has been updated in this packet. After the
PCD5008 has been turned on, this bit is set when the first
synchronization words are found (SM changes to 1) or
when the first synchronization search period (meaning the
receiver is active during this time) expires (SM stays 0),
after the PCD5008 is turned on. The latter condition gives
the host the option of assuming the paging device is in
range when it is turned on, and displaying out-of-range
only after the initial search period expires. After the initial
synchronous mode update, the SMU bit is set whenever
the PCD5008 switches from/to synchronous mode. The bit
is cleared when read. Changes in the SM bit due to turning
off the PCD5008 does not set the SMU bit. This bit is
initialized to 0 when the PCD5008 is reset.
LB:
low battery (Table 12). Set to the value last read from
the LOBAT pin. The host controls when the LOBAT pin is
read via the receiver control packets. This bit is initialized
to 0 at reset. It is also initialized to the inverse of the
LBP bit in the configuration packet, when the PCD5008 is
turned on, by setting the ON bit in the control packet.
LBU:
low battery update (Table 12). This bit is set if the
value on two consecutive reads of the LOBAT pin yielded
different results. The bit is cleared when read. The host
controls when the LOBAT pin is read via the receiver
control packets. Changes in the LB bit due to turning on
the PCD5008 do not cause the LBU bit to be set. This bit
is initialized to 0 when the PCD5008 is reset.
MT:
minute time-out (Table 12). Set if one minute has
elapsed. The bit is cleared when read. This bit is initialized
to 0 when the PCD5008 is reset.
EOF:
end of frame (Table 12). Set when the PCD5008 is
in all frame mode (AFM) (Section 8.8.3), and the end of
the frame has been reached. The PCD5008 is in the AFM
if the AFM enable counter is non-zero, if any temporary
address enabled (TAE) counter is non-zero (Section 8.8.3)
or if the FAF bit in the AFM packet is set. The bit is cleared
when read and initialized to 0 when the PCD5008 is reset.
BOE:
buffer overflow error (Table 12). Set when
information has been lost owing to slow host response
time. When the PCD5008 detects that its SPI transmit
buffer has overflowed, it clears the transmit buffer, turns off
decoding by clearing the ON bit in the control packet, and
sets this bit. The bit is cleared when read. This bit is
initialized to 0 when the PCD5008 is reset.
x:
unused bits (Table 12). The value of these bits is not
guaranteed.
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參數(shù)描述
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PCD5013H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX roaming decoder II
PCD5032 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ADPCM CODEC for digital cordless telephones
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