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參數(shù)資料
| 型號： | PCD5008H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | FLEX Pager Decoder |
| 中文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 19/64頁 |
| 文件大?。?/td> | 341K |
| 代理商： | PCD5008H |
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1998 Jun 17
19
Philips Semiconductors
Product specification
FLEX
Pager Decoder
PCD5008
8.4.7
C
ONTROL PACKET
(ID = 02H)
The control packet defines a number of different control
bits for the PCD5008.
FF:
force frame 0 to 7 (Table 11). When set, each of these
bits forces the PCD5008 to decode one of the FLEX
frames 0 to 7 irrespective of the system collapse value (for
details of collapse values see Section 8.6.2). For example,
if the system collapse causes the PCD5008 to decode
frames 0, 32, 64 and 96, setting FF
2
causes the PCD5008
to also decode FLEX
frame 2. This may be used to
acquire transmitted time information. Value after reset = 0.
SPM:
single phase mode (Table 11). When this bit is set,
the PCD5008 decodes only one of the transmitted phases.
When this bit is clear, the PCD5008 decodes all
transmitted phases. This value is determined by the
CAPCODE (Section 8.6). A change to this bit while the
PCD5008 is on does not take effect until the next block 0
of a frame. Value after reset = 0.
PS:
phase select (Tables 10 and 11). When the SPM bit is
set, these bits define which phase the PCD5008 shall
decode. This value is determined by the CAPCODE
(Section 8.6). A change to these bits, while the PCD5008
is on, does not take effect until the next block 0 of a frame.
Value after reset = 0.
Table 10
Phase selection (PS bits)
SBI:
send block information words (BIW) 2 to 4
(Table 11). When this bit is set, BIWs with time and date
information and BIWs received in error are sent to the host,
(Section 8.7.9). Value after reset = 0.
PS
1
PS
0
DECODED PHASE (BASED ON
FLEX
DATA RATE)
1600 bits/s 3200 bits/s 6400 bits/s
0
0
1
1
0
1
0
1
A
A
A
A
A
A
C
C
A
B
C
D
MTC:
minute timer clear (Table 11). Setting this bit causes
the 1-minute timer to restart from 0 (Section 8.4.8).
ON:
turn on decoder (Table 11). When this bit is set, the
PCD5008 decodes FLEX
signals. If this bit is cleared,
signal processing stops. However, to assure proper
operation, the PCD5008 requires that it be set into
asynchronous mode when turned off. To achieve that the
following sequence must be used:
1.
Send control packet with ON bit clear (decoder off)
2.
Send control packet with ON bit set (decoder on)
3.
Send control packet with ON bit clear (decoder off).
Timing between these steps is specified below and is
measured from the positive edge of the last clock of one
packet to the positive edge of the last clock of the next
packet.
The minimum time between steps 1 and 2 is the greater
of 2 ms or the programmed shut-down time.
The programmed shut-down time is the sum of all of the
times programmed in the used receiver shut-down
settings packets.
There is no maximum time between steps 1 and 2
The minimum time between steps 2 and 3 is 2 ms
The maximum time between steps 2 and 3 is the
programmed warm-up time minus 2 ms.
The programmed warm-up time is the sum of all the
times programmed in the used receiver warm-up
settings packets.
8.4.8
O
PERATING THE
1-
MINUTE TIMER
The PCD5008 provides a 1-minute timer which allows the
host to implement a time-of-day function while maintaining
low-power operation. The 1-minute timer is enabled using
the MTE bit in the configuration packet (Section 8.4.4).
When the 1-minute timer is enabled, a status packet is
sent at 1-minute intervals with the MT bit set
(Section 8.4.9). When the MTE bit is clear, the internal
1-minute timer stops counting. When the host sends a
control packet with MTC bit set, the 1-minute timer restarts
from 0. This allows accurate setting of a time-of-day
function.
Table 11
Control packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
1
0
FF
7
0
0
FF
6
SPM
SBI
FF
5
PS
1
0
FF
4
PS
0
MTC
FF
3
0
0
FF
2
0
0
FF
1
0
0
FF
0
0
ON
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|---|---|
| PCD5013 | FLEX roaming decoder II |
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| PCD5032 | ADPCM CODEC for digital cordless telephones |
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| PCD5032T | ADPCM CODEC for digital cordless telephones |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5008HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5013 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX roaming decoder II |
| PCD5013H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX roaming decoder II |
| PCD5032 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ADPCM CODEC for digital cordless telephones |
| PCD5032B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Linear CODEC |
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