參數(shù)資料
型號: PCD5002A
廠商: NXP Semiconductors N.V.
英文描述: Enhanced Pager Decoder for APOC1/POCSAG
中文描述: 增強(qiáng)傳呼機(jī)解碼器APOC1/POCSAG
文件頁數(shù): 39/48頁
文件大?。?/td> 252K
代理商: PCD5002A
1999 Jan 08
39
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Receiver control
t
RXT
t
RXON
RXE and ROE transition time
RXE establishment time
(nominal values: actual duration
is bit rate dependent, see
Table 25)
C
L
= 5 pF
SPF byte 01H; bits
D1 and D0 = 0 0
D1 and D0 = 0 1
D1 and D0 = 1 0
D1 and D0 = 1 1
SPF byte 01H; bits
D3 and D2 = 0 0
D3 and D2 = 0 1
D3 and D2 = 1 0
D3 and D2 = 1 1
100
ns
5
10
15
30
ms
ms
ms
ms
t
ROON
ROE establishment time
(nominal values: actual duration
is bit rate dependent, see
Table 25)
20
30
40
50
ms
ms
ms
ms
I
2
C-bus interface
f
SCL
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
r
t
f
C
B
t
SU;STA
t
HD;STA
t
SU;STO
SCL clock frequency
SCL clock low period
SCL clock HIGH period
data set-up time
data hold time
SDA and SCL rise time
SDA and SCL fall time
capacitive bus line load
START condition set-up time
START condition hold time
STOP condition set-up time
0
4.7
4.0
250
500
4.7
4.0
4.0
100
1000
300
400
kHz
μ
s
μ
s
ns
ns
ns
ns
pF
μ
s
μ
s
μ
s
Reset
t
RST
t
RSU
t
OSU
external reset duration
set-up time after reset
set-up time after switch-on
50
105
4
μ
s
μ
s
ms
oscillator running
oscillator running
Data input
t
TDI
t
DI1
t
DI0
data input transition time
data input logic 1 duration
data input logic 0 duration
see Fig.15
see Fig.15
see Fig.15
t
BIT
t
BIT
100
μ
s
POCSAG data timing (512 bits/s)
f
DI
t
BIT
t
CW
t
PA
t
BAT
data input rate
bit duration
code-word duration
preamble duration
batch duration
SPF byte 01H; D5 = 0; D4 = 0
1125
512
1.9531
62.5
1062.5
bits/s
ms
ms
ms
ms
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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