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參數(shù)資料
| 型號： | PCD5002A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for APOC1/POCSAG |
| 中文描述： | 增強傳呼機(jī)解碼器APOC1/POCSAG |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 252K |
| 代理商： | PCD5002A |
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1999 Jan 08
31
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
8.60
Synthesizer programming data
Data for programming a PLL synthesizer via pins ZSD,
ZSC and ZLE can be stored in row 1 of the EEPROM.
Six bytes are available starting with address 08H.
Data is transferred in two serial blocks of 24 bits each,
starting with bit 0 (MSB) of block 1. Any unused bits must
be programmed at the beginning of a block.
Table 28
Synthesizer programming data (EEPROM
address 08H to 0DH)
8.61
Identifier storage allocation
Up to 6 different identifiers can be stored in EEPROM for
matching with incoming data. The PCD5002A can
distinguish two types of identifiers:
User addresses (RIC)
User Programmable Sync Words (UPSW)
Batch zero identifiers
Continuous Data Decoding (CDD) sync words.
ADDRESS
(HEX)
BIT
(MSB: D7)
DESCRIPTION
08
D7 to D0
bits 0 to 7 of data block 1
(bit 0 is MSB)
bits 8 to 15
bits 16 to 23
bits 0 to 7 of data block 2
(bit 0 is MSB)
bits 8 to 15
bits 16 to 23
09
0A
0B
D7 to D0
D7 to D0
D7 to D0
0C
0D
D7 to D0
D7 to D0
Identifiers are stored in EEPROM rows 2, 3 and 4. Each
identifier location consists of 3 bytes in the same column.
The identifier number is equal to the column number + 1.
Each identifier can be individually enabled. The standard
POCSAG sync word is always enabled and has identifier
number 7.
The identifier type is determined by bits D2 and D0 of
identifier byte 3, as shown in Table 31.
Identifiers 1 and 2 always represent RICs or batch zero
identifiers. The last 4 identifiers (numbers 3 to 6) can
represent any identifier type.
A UPSW represents an unused address and must differ by
more than 6 bits from preamble to guarantee detection.
A batch zero identifier marks the start of a new cycle in the
APOC1 protocol. It is only recognized when APOC1
decoding has been enabled (SPF byte 00, bit D0).
Reception of a CDD sync word initiates continuous data
decoding. CDD sync words are only recognized when
continuous data decoding has been enabled
(SPF byte 00, bit 6).
Table 29 shows the memory locations of the 6 identifiers.
The bit allocation per identifier is given in Table 30.
Table 29
Identifier storage allocation (EEPROM address 10H to 25H)
ADDRESS (HEX)
BYTE
DESCRIPTION
10 to 15
18 to 1D
20 to 25
1
2
3
identifier number 1 to 6
identifier number 1 to 6
identifier number 1 to 6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD5002AH | Enhanced Pager Decoder for APOC1/POCSAG |
| PCD5002HBD-S | Telecommunication Decoder |
| PCD5002HBD-T | Telecommunication Decoder |
| PCD5003HB-T | Telecommunication Decoder |
| PCD5008HBD-T | Telecommunication Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5002AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for APOC1/POCSAG |
| PCD5002H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
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