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參數(shù)資料
| 型號(hào)： | PCD5002A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for APOC1/POCSAG |
| 中文描述： | 增強(qiáng)傳呼機(jī)解碼器APOC1/POCSAG |
| 文件頁數(shù)： | 22/48頁 |
| 文件大小： | 252K |
| 代理商： | PCD5002A |
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1999 Jan 08
22
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
8.30
Status/control register
The status/control register consists of two independent registers, one for reading (status) and one for writing (control).
The status register shows the current operating condition of the decoder and the cause(s) of an external interrupt.
The control register activates/deactivates certain functions. Tables 17 and 18 show the bit allocations of both registers.
All status bits will be reset after a status read operation except for the out-of-range, battery-low and receiver enable
indicator bits (see note 1 to Table 17).
Table 17
Status register (00H; read)
Note
1.
After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is
pending. D2 is reset when the RAM is empty (read and write pointers equal).
Table 18
Control register (00H; write)
BIT
(1)
VALUE
DESCRIPTION
D1 and D0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
1
1
1
no new call data
new call received (POCSAG or APOC1)
continuous decoding data available
batch zero data available (APOC1)
no data to be read (default after reset)
RAM read/write pointers different; data to be read
RAM read/write pointers equal; no more data to read
RAM buffer full or overflow
alert time-out expired
out-of-range
BAT input HIGH or RXE output active (selected by control bit D2)
periodic timer interrupt
D3 and D2
D4
D5
D6
D7
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
1
1
0
1
1
0
1
1
1
1
forced call termination (automatically reset after termination)
EEPROM programming enable
BAT input selected for monitoring (status bit D6)
RXE output selected for monitoring (status bit D6)
receiver continuously enabled (RXE = 1 and ROE = 1)
decoder in OFF status (while DON = 0)
decoder in ON status
out-of-range interrupt masked
BAT/RXE monitor interrupt masked
Periodic Timer interrupt masked
D2
D3
D4
D5
D6
D7
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| PCD5002AH | Enhanced Pager Decoder for APOC1/POCSAG |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5002AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for APOC1/POCSAG |
| PCD5002H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
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