參數(shù)資料
型號： PCD5002A
廠商： NXP Semiconductors N.V.
英文描述： Enhanced Pager Decoder for APOC1/POCSAG
中文描述： 增強傳呼機解碼器APOC1/POCSAG
文件頁數(shù)： 3/48頁
文件大?。?/td> 252K
代理商： PCD5002A
1999 Jan 08
3
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
1
FEATURES
Wide operating supply voltage range: 1.5 to 6.0 V
EEPROM programming requires only 2.0 V supply
Low operating current: 50
μ
A typ. (ON), 25
μ
A typ.
(OFF)
Temperature range
25 to +70
°
C
“CCIR radio paging Code No. 1”(POCSAG) compatible
Supports Advanced Pager Operator’s Code Phase 1
(APOC1) for extended battery economy
512, 1200 and 2400 bits/s data rates using 76.8 kHz
crystal
Built-in data filter (16 times oversampling) and bit clock
recovery
Advanced ACCESS
synchronization algorithm
2-bit random and (optional) 4-bit burst error correction
Up to 6 user addresses Receiver Identity Codes (RICs),
each with 4 functions/alert cadences
Optional automatic call termination when bit error rate is
high
Up to 6 user address frames, independently
programmable
Standard POCSAG sync word, plus up to 4 user
programmable sync words
Continuous data decoding upon reception of user
programmable sync word (optional)
Received data inversion (optional)
Call alert via beeper, vibrator or LED
2-level acoustic alert using single external transistor
Alert control: automatic (POCSAG type), via cadence
register or alert input pin
Separate power control of receiver and RF oscillator for
battery economy
Dedicated pin for easy control of superheterodyne
receiver
Synthesizer set-up and control interface (3-line serial)
On-chip EEPROM for storage of user addresses (RICs),
pager configuration and synthesizer data
On-chip SRAM buffer for message data
Slave I
2
C-bus interface to microcontroller for transfer of
message data, status/control and EEPROM
programming (data transfer at up to 100 kbits/s)
Wake-up interrupt for microcontroller, programmable
polarity
Direct and I
2
C-bus control of operating status (ON/OFF)
Battery-low indication (external detector)
Out-of-range condition indication
Real-time clock reference output
On-chip voltage doubler
Interfaces directly to UAA2080 and UAA2082 paging
receivers.
2
APPLICATIONS
Advanced display pagers (POCSAG and APOC1)
Basic alert-only pagers
Information services
Personal organizers
Telepoint
Telemetry/data transmission.
3
GENERAL DESCRIPTION
The PCD5002A is a very low power pager decoder and
controller, capable of handling both standard POCSAG
and the advanced APOC1 code. Continuous data
decoding upon reception of a dedicated sync word is
available for news pager applications.
Data rates supported are 512, 1200 and 2400 bits/s using
a single 76.8 kHz crystal. On-chip EEPROM is
programmable using a minimum supply voltage of 2.0 V,
allowing ‘over-the-air’ programming. I
2
C-bus compatible.
4
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
LQFP32 plastic low profile quad flat package; 32 leads; body 7
×
7
×
1.4 mm
DESCRIPTION
VERSION
PCD5002AH
SOT358-1
相關(guān)PDF資料
PDF描述
PCD5002AH Enhanced Pager Decoder for APOC1/POCSAG
PCD5002HBD-S Telecommunication Decoder
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCD5002AH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for APOC1/POCSAG
PCD5002H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder
PCD5002HBD-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder
PCD5002HBD-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder
PCD5002U/10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder
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