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參數(shù)資料
| 型號： | PCD5002A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for APOC1/POCSAG |
| 中文描述： | 增強(qiáng)傳呼機(jī)解碼器APOC1/POCSAG |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 252K |
| 代理商： | PCD5002A |
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1999 Jan 08
18
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
8.23
External receiver control and monitoring
An external controller may enable the receiver control
outputs continuously via an I
2
C-bus command, overruling
the normal enable pattern. Data reception continues
normally. This mode can be exited by means of a reset or
an I
2
C-bus command.
External monitoring of the receiver control output RXE is
possible via bit D6 in the status register, when enabled via
the control register (D2 = 1). Each change of state of
output RXE will generate an external interrupt at output
INT.
8.24
Battery condition input
A logic signal from an external sense circuit, signalling
battery condition, can be applied to the BAT input. This
input is sampled each time the receiver is disabled
(RXE
↓
0).
When enabled via the control register (D2 = 0), the
condition of input BAT is reflected in bit D6 of the status
register. Each change of state of bit D6 causes an external
interrupt at output INT.
When using the UAA2080 pager receiver a battery-low
condition corresponds to a logic HIGH level. With a
different sense circuit the reverse polarity can be used as
well, because every change of state is signalled to an
external controller.
After a reset the initial condition of the battery-low indicator
in the status register is zero.
8.25
Synthesizer control
Control of an external frequency synthesizer is possible
via a dedicated 3-line serial interface (outputs ZSD, ZSC
and ZLE). This interface is common to a number of
available synthesizers. The synthesizer is enabled using
the oscillator enable output ROE.
The frequency parameters must be programmed in
EEPROM. Two blocks of maximum 24 bits each can be
stored. Any unused bits must be programmed at the
beginning of a block: only the last bits are used by the
synthesizer.
When the function is selected by SPF programming
(SPF byte 1, bit D6), data is transferred to the synthesizer
each time the PCD5002A is switched from the OFF to the
ON status. Transfer takes place serially in two blocks,
starting with bit 0 (MSB) of block 1 (see Table 28).
Data bits on ZSD change on the falling edges of ZSC. After
clocking all bits into the synthesizer, a latch enable pulse
copies the data to the internal divider registers. A timing
diagram is illustrated in Fig.7.
The data output timing is synchronous, but has a pause in
the bitstream of each block. This pause occurs in the
13th bit while ZSC is LOW. The nominal pause duration t
p
depends on the programmed bit rate for data reception
and is shown in Table 15. The total duration of the 13th bit
is given by t
ZCL
+ t
p
.
A similar pause occurs between the first and the second
data block. The delay between the first latch enable pulse
and the second data block is given by t
ZDL2
+ t
p
.
The complete start-up timing of the synthesizer interface is
illustrated in Fig.14.
Table 15
Synthesizer programming pause
8.26
Serial microcontroller interface
The PCD5002A has an I
2
C-bus serial microcontroller
interface capable of operating at 400 kbits/s.
The PCD5002A is a slave transceiver with a 7-bit I
2
C-bus
address 39 (bits A6 to A0 = 0100111).
Data transmission requires 2 lines: SDA (data) and SCL
(clock), each with an external pull-up resistor. The clock
signal (SCL) for any data transmission must be generated
by the external controlling device.
A transmission is initiated by a START condition
(S: SCL = 1, SDA =
↓
) and terminated by a STOP
condition (P: SCL = 1, SDA =
↑
).
Data bits must be stable when SCL is HIGH. If there are
multiple transmissions, the STOP condition can be
replaced with a new START condition.
Data is transferred on a byte basis, starting with a device
address and a read/write indicator. Each transmitted byte
must be followed by an acknowledge bit A (active LOW).
If a receiving device is not ready to accept the next
complete byte, it can force a bus wait state by holding SCL
LOW.
The general I
2
C-bus transmission format is illustrated in
Fig.6. Formats for master/slave communication are
illustrated in Fig.9.
BIT RATE (bits/s)
t
p
(CLOCKS)
119
33
1
t
p
(
μ
s)
1549
430
13
512
1200
2400
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5002AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for APOC1/POCSAG |
| PCD5002H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
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